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From: Computer Breezer on 30 Dec 2006 16:19
Dear All,
May you be kind enough to tell me how can we build a 2-input NAND gate
with rise propagation delay= fall propagation delay= delay of a unit
inverter??

Your help is highly appreciated,
Regards

From: Del Cecchi on 30 Dec 2006 19:49

"Computer Breezer" <aoun.alexandre(a)gmail.com> wrote in message
news:1167513559.692766.49300(a)v33g2000cwv.googlegroups.com...
> Dear All,
> May you be kind enough to tell me how can we build a 2-input NAND gate
> with rise propagation delay= fall propagation delay= delay of a unit
> inverter??
>
> Your help is highly appreciated,
> Regards
>
It is quite simple. Since the Nfets are in series and the pfets are in
parallel, the nfets need to be twice as wide as the pfets.

pp
n
n

is the topology.

And since there are twice as many devices the pfets need to have width
twice that of the "unit inverter".

del


From: Rob Warnock on 31 Dec 2006 05:41
Del Cecchi <delcecchiofthenorth(a)gmail.com> wrote:
+---------------
| "Computer Breezer" <aoun.alexandre(a)gmail.com> asked:
| > May you be kind enough to tell me how can we build a 2-input NAND gate
| > with rise propagation delay= fall propagation delay= delay of a unit
| > inverter??
|
| It is quite simple. Since the Nfets are in series and the pfets are in
| parallel, the nfets need to be twice as wide as the pfets.
| pp
| n
| n
| is the topology.
| And since there are twice as many devices the pfets need to have width
| twice that of the "unit inverter".
+---------------

With the NAND's n-FETs twice as wide as the NAND's p-FETs
which are twice as wide as an inverter's FETs, doesn't the
increase in parasitic capacitance make such a NAND at least
a *little* slower than the inverter? So don't you need to
make the NAND's FETs even wider than the simple 4x/2x scaling
you mention?


-Rob

-----
Rob Warnock <rpw3(a)rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607

From: Del Cecchi on 31 Dec 2006 15:14

"Rob Warnock" <rpw3(a)rpw3.org> wrote in message
news:yu2dnXAiR6BpDgrYnZ2dnUVZ_u6rnZ2d(a)speakeasy.net...
> Del Cecchi <delcecchiofthenorth(a)gmail.com> wrote:
> +---------------
> | "Computer Breezer" <aoun.alexandre(a)gmail.com> asked:
> | > May you be kind enough to tell me how can we build a 2-input NAND
> gate
> | > with rise propagation delay= fall propagation delay= delay of a
> unit
> | > inverter??
> |
> | It is quite simple. Since the Nfets are in series and the pfets are
> in
> | parallel, the nfets need to be twice as wide as the pfets.
> | pp
> | n
> | n
> | is the topology.
> | And since there are twice as many devices the pfets need to have
> width
> | twice that of the "unit inverter".
> +---------------
>
> With the NAND's n-FETs twice as wide as the NAND's p-FETs
> which are twice as wide as an inverter's FETs, doesn't the
> increase in parasitic capacitance make such a NAND at least
> a *little* slower than the inverter? So don't you need to
> make the NAND's FETs even wider than the simple 4x/2x scaling
> you mention?
>
>
> -Rob
>
> -----
> Rob Warnock <rpw3(a)rpw3.org>
> 627 26th Avenue <URL:http://rpw3.org/>
> San Mateo, CA 94403 (650)572-2607
>
maybe you are right. Probably depends on the loading as well. Gate
limited delay, or fixed wire load would make a difference to a small
degree. But I'm not running spice or asx for some guy on usenet.

del


From: Rob Warnock on 31 Dec 2006 22:34
Del Cecchi <delcecchiofthenorth(a)gmail.com> wrote:
+---------------
| "Rob Warnock" <rpw3(a)rpw3.org> wrote:
| > ...increase in parasitic capacitance... don't you need to
| > make the NAND's FETs even wider than the simple 4x/2x scaling...
|
| maybe you are right. Probably depends on the loading as well. Gate
| limited delay, or fixed wire load would make a difference to a small
| degree. But I'm not running spice or asx for some guy on usenet.
+---------------

Wasn't asking for that. It's just that it's been a long time since
I had to deal with any gate-level layout issues and I thought I'd
just hijack his homework question to see if I still understood the
basics and maybe learn something new myself. ;-} ;-}

Anyway, while I'm here, to all I say:

*** HAPPY NEW YEAR!! ***


-Rob

-----
Rob Warnock <rpw3(a)rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607

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