Synthesis Comparison
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From: Moikel on 19 Apr 2008 18:09 Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural network. I have created two versions of the design; a serial and a parallel version. Both synthesise and work in hardware. I am comparing the two in terms of performance. I would also like to compare them in terms of how much FPGA resources they consume. Could somebody please give me some advice on what elements of synthesis would be good for comparison? I'm currently comparing Max Clock. Frequency, Number of Slices, Number of Bonded IOBs. Thanks
From: Mike Treseler on 19 Apr 2008 18:13 Moikel wrote: > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > of Bonded IOBs. I like Fmax, LUTs, and Flops. -- Mike Treseler
From: KJ on 21 Apr 2008 08:03 On Apr 19, 6:09 pm, Moikel <obviouslyadu...(a)gmail.com> wrote: > Hello, > > I am writing my report on a university project. The project work > involved an FPGA implementation of a neural network. > > I have created two versions of the design; a serial and a parallel > version. Both synthesise and work in hardware. > > I am comparing the two in terms of performance. I would also like to > compare them in terms of how much FPGA resources they consume. Could > somebody please give me some advice on what elements of synthesis > would be good for comparison? > > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > of Bonded IOBs. > > Thanks Be careful when measuring 'Number of Slices' or 'number of flip flops' or any other internal resource count, they can be misleading when used as a metric for design comparisons. The problem with these is that synthesis will often replicate logic or not optomize things as small as they 'could' be (generally they do this in order to get better clock speed performance), because they don't need to in order to meet the design requirements. From the perspective of synthesis software, meeting design requirements means simply: - It fits in the selected device - It runs at the selected clock speed(s). One way to get a reasonable estimate of internal resource usage is to target the design to something intentionally too small so that, no matter how hard synthesis works, the design won't fit. Then the software will tell you how many slices/flops/etc. that it is trying to fit, this number is frequently different than the numbers you will gets when it targets a larger device that the design actually will fit into. In one recent test case, the difference was 16% of the design. Kevin Jennings
From: Kolja Sulimma on 21 Apr 2008 08:53 On 20 Apr., 00:13, Mike Treseler <mike_trese...(a)comcast.net> wrote: > Moikel wrote: > > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > > of Bonded IOBs. > > I like Fmax, LUTs, and Flops. Yes, slices is meaningless. The number of slices can vary by a factor of two for the same synthesis result. Instead report DFFs and LUTs, and also note the number of inputs to a lut your target technology uses. Kolja Sulimma
From: KJ on 21 Apr 2008 11:26
On Apr 21, 8:53 am, Kolja Sulimma <ksuli...(a)googlemail.com> wrote: > > Instead report DFFs and LUTs, and also note the number of inputs to a > lut your target technology uses. > DFFs and LUTs are not necessarily good metrics either since they can be affected quite a bit by efforts to meet timing (i.e. register replication) and/or lack of efforts to optomize logic (if it doesn't entire fill up the device, synthesis might not try to do any better unless forced to in order to improve timing). KJ |