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From: jeffery_dong on 29 Mar 2008 19:09
On Feb 18, 5:20 pm, bigyellow <bigyel...(a)gmail.com> wrote:
> Hello,
>
> Does anybody have experience on writing TCL testcase in Modelsim? I
> only have VHDL simulation license of Modelsim, I used to write both
> testbench and testcase in VHDL. But I feel VHDL is not that nice to
> implement testcase.
>
> So I am thinking to implement my testbench in VHDL, and write the
> testcases in TCL for my next project. Of course the verification
> should be self-checking.
>
> Does it sounds feasible? How is the simulation speed?  Can anyone give
> me some reference?  Thanks in advance.
>
> -Best Regards
> Jim

Dear Jim,

Have you solve the problem? I also had such idea.
Our method is like yours. Testbench written in VHDL (I am using System
Verilog now), and the test case are text based command. I want to add
TCL script in the test case.

I think we are using an advanced method in the simulation
(verifiation). Hope we can keep touch.

My email addres : jeffery_dong(a)hotmail.com

Thanks

Jeffery
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