VHDL : Use concatenation on port mapping
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From: Georgios Sidiropoulos on 10 Oct 2005 06:51 Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);
From: Georgios Sidiropoulos on 10 Oct 2005 06:52 Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);
From: ALuPin on 10 Oct 2005 10:04 You could use some concurrent assignment in which you perform the concatenation. PORT MAP ( data => ls_data_concat ....) ls_data_concat <= (CAV & DAV & KDATA); Rgds André
From: Simon Peacock on 11 Oct 2005 04:27 you can't concat there.. you have to do it to another variable first Simon "Georgios Sidiropoulos" <me00569(a)cc.uoi.gr> wrote in message news:ee90b4d.0(a)webx.sUN8CHnE... > Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);
From: Jim Lewis on 12 Oct 2005 22:51
Georgios Sidiropoulos wrote: > Can someone use logic operations or concatenation > within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, -- illegal. see below use ranges wren => CAV or DAV, -- illegal. maybe in VHDL-2006 wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0 ); Slicing arrays (of course insert the correct dimensions): PacketRAM: packet_dpram PORT map ( data(3 downto 0) => CAV, data(7 downto 4) => DAV, data(15 downto 8) => KDATA, When doing this, always map all elements of data and map all elements of data consecutively. Cheers, Jim P.S. You might also try posting in comp.lang.vhdl for VHDL questions. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim(a)SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |