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From: c d saunter on 19 Jun 2008 08:32
Greetings All,

I've just spent 20 mins editing 12 VHDL files to add two signals and route
them up and down a design hierarchy.

Tedious and not exactly rocket science.

Is anyone aware of any refactoring tools out there to automate such
processes?

Regards,
Chris
From: Andy on 19 Jun 2008 08:55
On Jun 19, 7:32 am, christopher.saun...(a)durham.ac.uk (c d saunter)
wrote:
> Greetings All,
>
> I've just spent 20 mins editing 12 VHDL files to add two signals and route
> them up and down a design hierarchy.
>
> Tedious and not exactly rocket science.
>
> Is anyone aware of any refactoring tools out there to automate such
> processes?
>
> Regards,
> Chris

Well this method is not perfect, but it can help: Declare a record
type (either one and make all signals inout, or three for in, out,
inout) in a package and use that record type on the ports. Then you
can add/delete elements to the record by editing the package. This
typically works best for a bus or group of related signals that
typically go anywhere as a group. The entities may have multiple
record ports if they attach to multiple buses or signal groups.

It would be REALLY NICE if VHDL had user defined modes for record
types such that different elements of a record type port could have
different modes. Those user defined modes could then be used in a port
specification with a port of that type. You could define multiple
modes for the same type (i.e. master, slave for a bus).

Besides that, I strongly recommend not using components/configurations
if you do not need the configurability. Directly instantiate the
entity/architectures, and then you don't have any components or
configurations to keep up to date.

Andy
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