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From: Nicolas Matringe on 21 Apr 2008 02:32
Michael a �crit :

> So is a cast in VHDL just like a cast in C? I must admit this is the
> first I've heard of VHDL having that ability.

In VHDL you can only cast between "closely related types". You can not
cast an integer to a signed vector, for example. This requires a
conversion function.

In the previous example, I used a cast to convert an unsigned to a
std_logic_vector. This is allowed because both types are arrays of
std_logic.

Nicolas
From: Brian Drummond on 21 Apr 2008 07:55
On Sun, 20 Apr 2008 06:05:49 -0700 (PDT), Michael <nleahcim(a)gmail.com> wrote:

>On Apr 19, 10:41�pm, Frank Buss <f...(a)frank-buss.de> wrote:
>> Michael wrote:
>> > Hi there - I am slowly teaching myself VHDL this weekend. I am getting
>> > an error that I do not understand: "parse error, unexpected IF". My
>> > very simple code is at the bottom of this post, and the error is being
>> > caused by the "if switches(0)=0 then" line. Can somebody tell me what
>> > I'm doing wrong? I'm sure it's terribly simple - but coming from a C
>> > background I am having trouble understanding what I'm doing wrong.
>>
>> You can't use IF outside of processes, a bit like that you can't use the C
>> IF outside of functions. You could write it like this:
>>
>> led <= cnt(30 downto 23) when switches(0)=0 else enccnt;
>>
>> A bit like the ?-operator in C.
>
>Hi Frank - thanks for clearing that up. I had not realized that
>limitation of IF. Why can ifs only be used inside processes? That
>strikes me as an odd limitation, though I'm sure there's a good reason
>behind it.

It may be to remind you that - within a process - you can treat VHDL as a
programming language with all the limitations of sequential programming like C
(at least for simulation, though for synthesis you have to obey further
restrictions; e.g. no files!), but outside a process you are in a completely
different paradigm, closer to dataflow or functional programming (FP) languages,
where you can directly express parallelism (such as interactions between
sequential processes).

It's quite funny because with the arrival of multicore CPUs, the C programming
community (along with the rest of the sequential mindset) are talking like there
is some kind of crisis! They will either have to look back a quarter century or
so for solutions like Occam, CSP or even Ada's tasking, or adopt something more
like VHDL to exploit today's commodity CPUs to more than 1/4 of their capacity.

- Brian

From: Kevin Neilson on 21 Apr 2008 13:11
>> Second point : signal switches is an array of std_logic, not an array of
>> integers. std_logic litteral constants must be written betwen single quotes:
>> if switches(0) = '0' then
>> led <= std_logic_vector(led(30 downto 23));
>
> Ah - perfect! Adding those quotes just fixed one of my problems!
>
>> Since cnt is now unsigned, you need to cast it to std_logic_vector
>> before assigning to led.
>>
>> Nicolas
>
> So is a cast in VHDL just like a cast in C? I must admit this is the
> first I've heard of VHDL having that ability.
>
> Thanks!
>
> -Michael

Yes, my son--you are quickly learning the lameness of VHDL. A number
isn't a number--sometimes it must be in single quotes, sometimes in
double quotes, and most often expressed in binary, just as the ancients
used to write. And almost never can you use a number directly, but must
convert it from one arcane type to another. -Kevin
From: KJ on 21 Apr 2008 14:47
On Apr 21, 1:11 pm, Kevin Neilson
<kevin_neil...(a)removethiscomcast.net> wrote:

>
> Yes, my son--you are quickly learning the lameness of VHDL.  A number
> isn't a number--sometimes it must be in single quotes, sometimes in
> double quotes, and most often expressed in binary, just as the ancients
> used to write.  And almost never can you use a number directly, but must
> convert it from one arcane type to another.  -Kevin- Hide quoted text -
>

On the first day, the VHDL gods created 'integer', 'natural', etc. and
created ways to easily specify such numbers in any base, and saw that
it was good...and the VHDL gods said, go forth and use these types for
they are of my creation and they are good....but the unbelievers who
think every number will potentially be bigger than 32 bits on each and
every design that they create and the scallywags that created
std_logic_arith refused to use 'integer' and instead used
std_logic_vectors to perform arithmetic and then cursed the VHDL
language for the numerous type conversions that they themselves
brought down upon themselves....

KJ
From: HT-Lab on 22 Apr 2008 06:15

"KJ" <kkjennings(a)sbcglobal.net> wrote in message
news:4039fc88-3cab-46eb-b778-3d20001f14d6(a)d45g2000hsc.googlegroups.com...
On Apr 21, 1:11 pm, Kevin Neilson
<kevin_neil...(a)removethiscomcast.net> wrote:

>
> Yes, my son--you are quickly learning the lameness of VHDL. A number
> isn't a number--sometimes it must be in single quotes, sometimes in
> double quotes, and most often expressed in binary, just as the ancients
> used to write. And almost never can you use a number directly, but must
> convert it from one arcane type to another. -Kevin- Hide quoted text -
>
>
>On the first day, the VHDL gods created 'integer', 'natural', etc. and
>created ways to easily specify such numbers in any base, and saw that
>it was good...and the VHDL gods said, go forth and use these types for
>they are of my creation and they are good....but the unbelievers who
>think every number will potentially be bigger than 32 bits on each and
>every design that they create and the scallywags that created
>std_logic_arith refused to use 'integer' and instead used
>std_logic_vectors to perform arithmetic and then cursed the VHDL
>language for the numerous type conversions that they themselves
>brought down upon themselves....
>
>KJ

very good :-)

Hans
www.ht-lab.com



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