Virtex4 running at 360Mhz DDR
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From: Peter Alfke on 10 May 2005 18:33 "fastgreen2", your design looks just right for the Virtex-4 capabilities. Keep the pc-board data skew reasonable. You can use a DCM to divide the clock, or you can go with the CE scheme, whatever you prefer. Should work with a reasonable amount of attention to detail. Peter Alfke, Xilinx Applications (I passed this by several experts...)
From: Symon on 10 May 2005 19:10 "John_H" <johnhandwork(a)mail.com> wrote in message news:fyage.14$p%5.114(a)news-west.eli.net... > Look at > http://www.xilinx.com/products/virtex4/capabilities/selectio.htm#chipsync > and > > http://www.xilinx.com/products/design_resources/conn_central/resource/ssio_resources.htm > > for discussions on the 1 Gbit/s/pin Virtex-4 differential I/O and you may > get a better feel for the margins you can get in your design. > > If all your LVDS are at the same clock rate, the DCM skews shouldn't be a > problem and could easily be registered back to the slower domain if the > skews were an issue. > > Xilinx went to great lengths to make the Virtex-4 I/O capable of some pretty > high speeds without taxing the designer. > > You might also like to look at this link. http://www.altera.com/products/devices/stratix2/utilities/st2-signal_integrity.html?f=tchio&k=g3 Altera claims their parts have a better LVDS 'eye' because they have superior (i.e. less) pin capacitance. The capacitance gives a lot of ISI. I've been bitten by Xilinx FPGA pin capacitance before, albeit in a slightly different situation. I guess it's the inevitable consequence of trying to fit every possible I/O standard onto every pin. If I'm reading the page properly, Altera mitigate this by having different sets of pins which are capable of different I/O standards. Separate 'Rocket I/Os' also solve this problem. Of course, the OP's data rate is significantly lower than the rate shown in the link, so should be no problem! ;-) Cheers, Syms.
From: John_H on 10 May 2005 20:03 "Symon" <symon_brewer(a)hotmail.com> wrote in message news:42813fd3_2(a)x-privat.org... <snip> > You might also like to look at this link. > http://www.altera.com/products/devices/stratix2/utilities/st2-signal_integrity.html?f=tchio&k=g3 > > Altera claims their parts have a better LVDS 'eye' because they have > superior (i.e. less) pin capacitance. The capacitance gives a lot of ISI. <snip> But doesn't the Altera information use external LVDS terminations and monitor external to the part rather than internal terminations and the eye seen by the receiver? By looking outside the package that has an embedded differential termination, isn't the data skewed?
From: Symon on 10 May 2005 20:07 "Symon" <symon_brewer(a)hotmail.com> wrote in message news:4281198e$1_2(a)x-privat.org... > > > > - And how do you make the enable signal go on the global clock net? > > > You ask someone from Xilinx! I've not yet started my V4 design. I just > remembered that from the marketing spiel we had. > Cheers, Syms. > Hmmm, I might have given you a bum steer there. I just looked at the FPGA editor view of V4 and it seems there's NOT a path from the GBUFs to the CLB CE. You can control a CE pin on the GBUF, but that's about as useful as a chocolate teapot in this case. Sorry about that, Syms.
From: Symon on 10 May 2005 20:15
"John_H" <johnhandwork(a)mail.com> wrote in message news:OZbge.15$p%5.117(a)news-west.eli.net... > "Symon" <symon_brewer(a)hotmail.com> wrote in message > news:42813fd3_2(a)x-privat.org... > > <snip> > > > You might also like to look at this link. > > > http://www.altera.com/products/devices/stratix2/utilities/st2-signal_integrity.html?f=tchio&k=g3 > > > > Altera claims their parts have a better LVDS 'eye' because they have > > superior (i.e. less) pin capacitance. The capacitance gives a lot of ISI. > > <snip> > > But doesn't the Altera information use external LVDS terminations and > monitor external to the part rather than internal terminations and the eye > seen by the receiver? By looking outside the package that has an embedded > differential termination, isn't the data skewed? > > I don't think so John. I think the whole white paper is based on a simulation using the published Xilinx IBIS files. The terminations are simulated as being on-chip. The Figure 1. in this document:- http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf is in the mind of an IBIS simulator, I guess. So, there are no physical measurements. Their data doesn't surprise me; 12.5pF of pin capacitance will really screw with inter-symbol interference at Gbit rates. Best, Syms. |