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From: Symon on 11 May 2005 12:59 "Austin Lesea" <austin(a)xilinx.com> wrote in message news:d5t993$3041(a)cliff.xsj.xilinx.com... > > As for the reflection, the LVDS transmitter is also a 100 ohm > termination, so reflections are absorbed at the transmitter (when the > LVDS is properly done and meets the specifications, which ours do). > No. Not if this transmitter is a Xilinx FPGA with 12.5pF of parasitic capacitance. The high frequencies see a lower impedance, and so stuff relects back out of the transmitter, exactly the same as at the receiver. This is the point I'm trying to get you to understand. I tell you what, why don't you call that nice Dr. Howard Johnson and ask him? Here's a quote from National's LVDS manual. "In a good design the connector contributes 2 pF to 3 pF, the trace contributes 2 pF to 3 pF, and the device contributes 4 pF to 5 pF.The total load in such a design is around 10 pF. The flexibility of programmable devices comes at the cost of capacitance. National Bus LVDS products have an I/O capacitance of 5 pF. The I/O capacitance of a programmable device is approximately double or 10 pF. This increase in capacitance will lower the loaded bus impedance, thereby reducing the available noise margin and lowering the reliability of operation in the design." http://www.national.com/appinfo/lvds/files/ownersmanual.pdf > > Anyone with an IBIS simulator can see all of the above happening, so I > really don't want to take this any further - demanding to see scope > shots of things is pretty pointless when the simulations are perfectly > good (when they are done correctly). > I don't want to see scope shots, I agree I want to see a simulation 'done correctly'. I think I already have on Altera's website. Best regards, Syms.
From: Symon on 11 May 2005 13:05 "Ajay Roopchansingh" <ajaytr(a)donotspam_xilinx.com> wrote in message news:d5t9ck$30d1(a)cliff.xsj.xilinx.com... > > No you didn't bum steer... you were right initially. CE nets can be put > onto a global clock network. Look at the CLB switch box in FPGA Editor > again... each CE pin can be driven by a bounce pip (4 stubs in the > middle right edge of the switch box), and these 4 bounces can all be > driven by the GLK pips on the lower left edge of the switch box. > There's your path. > Doh, Thanks Ajay. I see it now. Sneaky! Cheers, Syms.
From: Philip Freidin on 11 May 2005 13:05 On Tue, 10 May 2005 19:02:19 -0700, austin <austin(a)xilinx.com> wrote: >The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but >can it be used in a real application on a real board? Make up your mind Austin. On numerous occasions you have recommended that people run simulation of I/O systems to see what should happen, and you have recommened the IBIS models. To suggest that Altera does not know how to run simulations is insulting. Enough! Philip Freidin =================== Philip Freidin philip.freidin(a)fpga-faq.org Host for WWW.FPGA-FAQ.ORG
From: Austin Lesea on 11 May 2005 13:12 Symon, What is 12.5pF in series with 12.5pF? Yes, that is right, 6.25pF differential load, not 12.5pF. Falling for the A FUD is especially embarrassing when you just repeat things which are factually incorrect. All these things are taken into account from the simulation. Austin
From: Austin Lesea on 11 May 2005 13:35
Philip, 1. They ignored the top comment lines of the IBIS model which instructs them how to model the package (since package modeling is incorrect and wrong in IBIS 3.2). 2. They used an external resistor instead of the internal termination. Run it right, or not at all. Austin |