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From: Symon on 11 May 2005 16:36 "Austin Lesea" <austin(a)xilinx.com> wrote in message news:d5teda$2vn1(a)cliff.xsj.xilinx.com... > Symon, > > What is 12.5pF in series with 12.5pF? > > Yes, that is right, 6.25pF differential load, not 12.5pF. > > Falling for the A FUD is especially embarrassing when you just repeat > things which are factually incorrect. > > All these things are taken into account from the simulation. > > Austin > OK, I'm not sure where that came from, but let me explain. Each pin of the pair is driven by a 50 ohm line. Taken together, these two 50 ohm lines make a 100 ohm differential pair. At one single pin you've got a 12.5pF capacitor being driven from 50 ohms. If you view the pair together, you've got 6.25pF driven by 100 ohms. The return loss is the same in both cases. As is the rise time (RC = 625ps). So, Altera's 6.1pF per pin turns into 3.05pF when viewed as the termination to a pair. In the 1Gbit region, their return loss is much better. Their rise time is twice as fast. (RC=305ps). Now, pay attention. I can make your c(r)appy LVDS work better. Given the problem is that you've got a large Cpin because (I guess) of all the other attached goodies, a way to improve things is to drive this capacitance with a lower impedance. For an FPGA to FPGA connection, use a 50 Ohm differential transmission line instead of 100 Ohms. If you place an extra external 100 Ohms differential termination resistor at _BOTH_ end of this t-line, you have a pretty well matched 50 Ohm connection. The pole caused by the parasitic capacitance has moved out to double the frequency it was at. Of course, the signal amplitude has halved, which tends to make the eye close vertically, but it will open horizontally, which is the limiting factor in this case. Maybe LVDS_EXT would be a good idea too. There are also other methods to open the eye for specific bitrates if the t-line characteristics and parasitics of the parts are known. You need to use an application specific filter at the end of the t-line. HTH, Syms.
From: Austin Lesea on 11 May 2005 17:12 Symon, All true. I would suggest that you should have more of a differential line, than two single ended 50 ohm lines, but it doesn't change anything at all (you still end up being differentially terminated at the receiver, with 6.25pF across 100 ohms). The eye is plenty good for up to 1 Gbs (see the ML450). It does not work up to 1.3 Gbs, because we didn't design it to work up to there: that is what the MGTs are for. If there is a 'beauty contest' for the 'best LVDS eye pattern', I will admit we come in second (due to increased Cpin), but I will not admit that it matters so far as use, function, or anything important is concerned. The Idly feature that allows for independent skew adjustment for each IO pin (pair) to center the eye sampling point to within +/-78ps is a far more useful feature than having 'pretty eyes'. Austin
From: Brian Davis on 11 May 2005 21:41 Symon wrote: > >Taken together, these two 50 ohm lines make a 100 ohm >differential pair. At one single pin you've got a >12.5pF capacitor being driven from 50 ohms. If you view >the pair together, you've got 6.25pF driven by 100 ohms. >The return loss is the same in both cases. As is the rise >time (RC = 625ps). So, Altera's 6.1pF per pin turns into >3.05pF when viewed as the termination to a pair. > nice explanation... Best wishes on getting Austin to stop with his "but it's really half, differentially" handwaving. I've tried before, with results similar to that "but it goes to Eleven" bit from "Spinal Tap". > >a way to improve things is to drive this capacitance >with a lower impedance > Also, when you've got plenty of drive margin, a differential attenuator ahead of the FPGA (with internal termination) works nicely to attenuate the reflection, and also makes for a convenient differential probe point. If you have 6dB to spare, even the most horrible of loads presents at least 12dB return loss, with the probe seeing 1/4 the reflection voltage of the original circuit.(however, the attenuator doesn't lower the drive impedance as does your suggestion ) Brian
From: Brian Davis on 11 May 2005 23:28 Austin, > >Lots of scope shots are available (ask your FAE). > Then why not publish them, along with a comparison of IBIS/HSPICE simulations versus the real world measurements? > >But, I am sure our Marketing Folks will be rolling our scope shots >as part of pitch-packs, etc. for those who are unable or unwilling >to do the SI engineering that their job requires of them. > Let's see if I've got this straight [1]: A) Xilinx publicly posts in FPGA and SI forums touting their real world X vs. A package testing, and asks for feedback [2] B) Forum users post some suggested measurements, which a certain Xilinx employee says they can make C) Two months later, when asked when said measurements might be published, the very same Xilinx employee cops an attitude > >Get the ML450 board, or ask for the documentation. > That would be the same manual (UG077 v1.2) that mentions a HyperTransport compliant DUT interface connector, without pointing out that the the specified V4 FPGA Cin is 5x the allowed HyperTransport max Cin for a 1 Gbps part ??? As to why that matters: a HyperTransport test probe attempting to monitor the input link to the FPGA can't function properly because Cin reflections off the FPGA would prevent the probe from properly clocking the data at the mid T-line probe sampling point. There are ways around this, but life would be easier if Xilinx actually bothered to meet the spec in the first place. Lacking that, proper documentation of your part's shortcomings, and how and when to work around them, would be appropriate. Brian [1] Speaking of those unable to perform the SI engineering that is required of them : when might we expect publication of characterized static DCI power and DCI impedance modulation limits for the five year old Virtex2 FPGA family ? [2] http://groups-beta.google.com/group/comp.arch.fpga/msg/d1004ae1fdca9825?hl=en
From: Austin Lesea on 12 May 2005 11:04
Brian, All I am trying to point out is that the load is 6.25pF + 100 ohms, not 12.5pF + 100 ohms. When folks wave their arms and state 12.5pF is the LVDS load, they are miss-stating it. Simple point. And once you do the simulations, or look at the actual waveforms, you realize that it is mostly just a beauty contest. In communications theory, excess bandwidth in the channel only adds to the error rate (due to noise). Some band limiting is a good thing. Too much is a bad thing (eg using the LVDS at 1.3 Gbs where it wasn't designed to be used, that is where our MGTs are to be used). Austin |