Virtex4 running at 360Mhz DDR
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From: Brian Davis on 15 May 2005 22:28 Austin, Which of the following posts regarding Cin is more helpful for both Xilinx and its' customers: Austin [1]: > > Use the internal one, and the capacitance does not matter > (do the sim yourself if you do not believe me). > Brian [2]: > > At no point have I claimed that the V2 inputs are unusable, > but only that, in the presence of high speed drivers, extra > engineering effort needs to be expended to both understand the > impact of the V2 input capacitance on the interconnect, and > find a work-around that is appropriate for the design at hand. > Austin wrote: > >When folks wave their arms and state 12.5pF is the LVDS load, >they are miss-stating it. > The only I/O capacitance number published in your datasheet is a single-ended parameter called Cin (or if you prefer, C_comp from the IBIS files). Quoting this published datasheet Cin value is perfectly valid, and does not require "correction". Comparing that number against the single ended Cin's of other devices, or against a single ended spec, is also perfectly valid. I have never said the differential load is 12.5 pf; it is clear from my posts that I understand this, and also understand that the assumption of Cdiff_effective = 1/2 Cin_single_ended applies only for the differential components of the signals on the Tline. I find it rather inconsistent that in past discussions of Xilinx's newly onerous SSO limits for the current mode output drivers, you've been quite insistent that real world paths are NOT perfectly balanced- Yet when discussing the effects of high Cin, you posit that everything is perfectly balanced back to a perfect source termination, so that a 50-60% voltage reflection off of your input pins is never a problem. If only all FPGA input buffers could live happily ever after there in Austin's world, where all connections are ideal differential point-point links, all drivers have perfect back terminations, and no probing or multidrops are ever allowed. > >In communications theory, excess bandwidth in the channel only adds >to the error rate (due to noise). Some band limiting is a good thing. > And massive, coherent input reflections do not fit the AWGN assumptions of most channel models, now do they? Brian p.s. As for your other post, I'll reply once I finish recovering from a hard drive crash at home and can find my old files again. [1] http://groups-beta.google.com/group/comp.arch.fpga/msg/57bbb3ea78e194ed?hl=en [2] http://groups-beta.google.com/group/comp.arch.fpga/msg/a044806f313848e6?hl=en
From: Paul Leventis (at home) on 16 May 2005 23:43 Hi Austin, Well, things are getting a little less busy with my day job, so I finally have time to start replying again... I figured I'd start with an easy one. > The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but > can it be used in a real application on a real board? Yes. Stratix II has LVDS running at 1.3 Gbps reliably across process, temperature, voltage. Beautiful eye diagrams. In simulation and on the board. And as noted here (http://www.altera.com/products/devices/stratix2/features/performance/st2-perf_improvements.html), we will be increasing the spec to 1.25 Gbps in an upcoming version of Quartus II. BTW, our simulations line up very will with board measurements. We offer accurate IBIS models that we proudly stand behind. Regards, Paul Leventis Altera Corp.
From: Paul Leventis (at home) on 17 May 2005 04:01 Austin: > I am suprised at you. Their white paper clearly shows the simualtion is > done with the external termination, and not the internal one. > Use the internal one, and the capacitance does not matter (do the sim > yourself if you do not believe me). According to our engineer who ran the sims, we did use on-chip termination for both V4 and Stratix II. I read the whitepaper again (http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf) and I can't find anywhere where it says we didn't use on-chip termination. > The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but > can it be used in a real application on a real board? Sorry to hammer on this again, but the above mentioned whitepaper does show some beautiful eye diagrams for SII and some ugly ones for V4. It also shows how nicely our lab measurement (of 1.3 Gbps LVDS on Stratix II) compares to the IBIS simulation. Regards, Paul Leventis Altera Corp.
From: fastgreen2000 on 17 May 2005 08:36 Wait a minute - don't oversimply the original design critera - 720Mbps DDR LVDS is only a part of my question. The design also needs to run the internals at 360Mhz, and that include portion of the fabric, not just DSP48, etc. Five years ago, I don't think so. Maybe in the lab somewhere, but not as an available product.
From: Austin Lesea on 17 May 2005 10:36
No problem. That is what all of the wonderful features are for in V4 (SSIO, IODLY, DCM, etc.). All of the above go a long way to support the fabric. Even though the fabric will run at 500 MHz, it is far easier to mux it down to 200 MHz, or 100 MHz (using the built in SSIO features) which makes place and route easier, and also provides a lot of margin. Just go buy the ML450 board (network interfaces), and you will get a fully working platform to test out all of your ~ 400 MHz up to 500 MHz DDR interfaces. Austin |