Virtex4 running at 360Mhz DDR
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From: Symon on 18 May 2005 19:29 "Paul Leventis (at home)" <paulleventis-news(a)yahoo.ca> wrote in message news:c9mdnXx_EujE9RTfRVn-2w(a)rogers.com... > > we will be increasing the spec to 1.25 Gbps in an upcoming version of > Quartus II. > Paul, Does that mean in Stratix II I could run an internal clock at 625MHz and use the I/O DDR to move data out at 1.25Gbps? Thanks, Syms.
From: Paul Leventis on 18 May 2005 20:46 Hi Symon, There is a hard serializer/deserializer circuitry available for the left and right LVDS I/O banks. These SERDES blocks allow you to deserialize/serialize by any factor between 4 and 10x. For example, you could bring in a 4x data bus running at 312.5 Mhz. Or you can bypass the SERDES block and use the DDR registers for a 2x SERDES. Or bypass completely for 1x... but not at 1.25 Gbps. I don't know what speed the SERDES/DDR I/O clock can run at or will run at when we update this specification. I'm sure it will be published at the time. We also have dedicated Dynamic Phase Alignment (DPA) circuitry for source-synchronous applications. The DPA block enables you to eliminate channel-to-channel and clock-to-channel skew. It achieves this by selecting the best clock phase to use for each I/O pair, centering the sampling window in the eye. Regards, Paul Leventis Altera Corp.
From: John M on 19 May 2005 09:13 Symon, According to the data sheet, you can run the LVDS I/O up to 500 MHz in the fastest speed grade part. That would get you 1 Gbps. More likely, you would use the SERDES. For example, at 130 MHz and using x8 serialization, you get 1.04 Gbps per pair. Here is a link to the DPA datasheet: http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf John
From: Symon on 19 May 2005 12:56 Paul and John, Thanks very much for your replies! So, for 1.25Gbps I'd need to use the SERDES. I guess that means I have to use the PLL circuit to make the clock? If I had more than 1 of these links, how easy is it to ensure that they're all synchronised together. For example, I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B I use the serdes to do this. Can I ensure that a_n appears at (more or less) the same time as b_n? I.e. that the shift registers in the two serdes are aligned? I know, I should read the bloody manual more carefully, but I couldn't find this on a first pass. Thanks, Syms. "Paul Leventis" <paul.leventis(a)utoronto.ca> wrote in message news:1116463566.371867.303600(a)g43g2000cwa.googlegroups.com... > Hi Symon, > > There is a hard serializer/deserializer circuitry available for the > left and right LVDS I/O banks. These SERDES blocks allow you to > deserialize/serialize by any factor between 4 and 10x. For example, > you could bring in a 4x data bus running at 312.5 Mhz. Or you can > bypass the SERDES block and use the DDR registers for a 2x SERDES. Or > bypass completely for 1x... but not at 1.25 Gbps. I don't know what > speed the SERDES/DDR I/O clock can run at or will run at when we update > this specification. I'm sure it will be published at the time. > > We also have dedicated Dynamic Phase Alignment (DPA) circuitry for > source-synchronous applications. The DPA block enables you to > eliminate channel-to-channel and clock-to-channel skew. It achieves > this by selecting the best clock phase to use for each I/O pair, > centering the sampling window in the eye. > > Regards, > > Paul Leventis > Altera Corp. >
From: Paul Leventis (at home) on 30 May 2005 23:23
Hi Symon, Sorry for taking so long to reply. > I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A > I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B > I use the serdes to do this. Can I ensure that a_n appears at (more or > less) > the same time as b_n? I.e. that the shift registers in the two serdes are > aligned? That's what the SERDES block is for. You just need to instantiate a altlvds_rx (receiver) or altlvds_tx (transmitter) with the number of channels you want in the link. Each of the channels will share a common PLL. Therefore, they share a common clock, and the enable pulses derived from that clock. And if you want to give the manual another stab ;-), I've been told that volume 2, chapter 5 of the Stratix II handbook, "High-Speed Differential I/O Interfaces with DPA in Stratix II Devices" http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf is helpful. Figures 5-2, 5-11 and 5-12 are most applicable in this case. Regards, Paul Leventis Altera Corp. |