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From: Goli on 14 Apr 2008 02:02
Hi,

Does anyone know if user defined Primitives are supported with XST, I
have the following code and it is giving error,

primitive mymultiplexer

(y, a, b, c0, c1, c2, c3);
output y;
// reg y;
input a, b, c0, c1, c2, c3;

table
// a b c0 c1 c2 c3 y
0 0 1 ? ? ? : 1 ;
0 0 0 ? ? ? : 0 ;
0 0 x ? ? ? : x ;
1 0 ? 1 ? ? : 1 ;
1 0 ? 0 ? ? : 0 ;
1 0 ? x ? ? : x ;
0 1 ? ? 1 ? : 1 ;
0 1 ? ? 0 ? : 0 ;
0 1 ? ? x ? : x ;
1 1 ? ? ? 1 : 1 ;
1 1 ? ? ? 0 : 0 ;
1 1 ? ? ? x : x ;
x 0 1 1 ? ? : 1 ;
x 0 0 0 ? ? : 0 ;
x 1 ? ? 1 1 : 1 ;
x 1 ? ? 0 0 : 0 ;
0 x 1 ? 1 ? : 1 ;
0 x 0 ? 0 ? : 0 ;
1 x ? 1 ? 1 : 1 ;
1 x ? 0 ? 0 : 0 ;
x x 0 0 0 0 : 0 ;
x x 1 1 1 1 : 1 ;
endtable


endprimitive

ISE reports: Unsupported Switch or UDP primitive.

I can work around this problem, but writing code as modules, but I was
just wondering if I have to enable something in the tool and get it
working.


From: Brian Drummond on 14 Apr 2008 09:17
On Sun, 13 Apr 2008 23:02:23 -0700 (PDT), Goli <togoli(a)gmail.com> wrote:

>Hi,
>
>Does anyone know if user defined Primitives are supported with XST, I
>have the following code and it is giving error,
>
>primitive mymultiplexer
....
>endprimitive
>
>ISE reports: Unsupported Switch or UDP primitive.
>
>I can work around this problem, but writing code as modules, but I was
>just wondering if I have to enable something in the tool and get it
>working.

The nearest to an "user defined primitive" is a "black box". You can start by
creating a module, and synthesise that module separately, (to a .ngc file)
ensuring that XST will not add I/O pins for that module. (There are options
settings to do that)

Then you can use that "black box" in your design. I don't do Verilog, but in
VHDL you attach a "box_type" attribute set to "black_box" to that component.
Verilog does it differently but I can't help with that. XST won't worry that the
insides of that module aren't defined, it will leave the black box empty.

The back end tools (Translate, MAP, PAR etc) need access to the .ngc file
created earlier for the module, to complete the design by filling in the "black
box". Typically you keep all your black boxes in either the project directory,
or a separate directory and set options for the "Translate" tool to find that
directory.

This is just a sketch of a solution; you will need to read Xilinx documentation
(and search for "black box") for more details. EDK uses this technique for
pre-compiled processor cores, but you can do the same thing yourself.

- Brian

From: mk on 14 Apr 2008 12:02
On Sun, 13 Apr 2008 23:02:23 -0700 (PDT), Goli <togoli(a)gmail.com>
wrote:

>Hi,
>
>Does anyone know if user defined Primitives are supported with XST, I
>have the following code and it is giving error,

UDPs are not synthesizable. You're better off using a behavioral
definition for the 4-1 mux you have. If your code depends on the fact
that when all inputs are the same, the output becomes that value
regardles of the select input, you can model that too but you have
remember to suppress it for synthesis.
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