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From: Gabor on 21 Apr 2008 17:03
On Apr 21, 4:09 pm, Kevin Neilson
<kevin_neil...(a)removethiscomcast.net> wrote:
> Jim Wu wrote:
> > On Apr 18, 11:32 pm, b...(a)hometoolong.inv wrote:
> >> I used the latest version of MIG to generate pinouts for a Virtex 4
> >> DDR2 interface. In addition to all the usual Address, Data, and
> >> Control I/Os, MIG assigned an I/O pin for a signal called
> >> SYS_RESET_IN_N. What is the function of this pin?
>
> This is off-topic, but the "_N" probably indicates that this is an
> active-low signal; I want to know why we still have new designs with
> active-low signals. Is it 1982? Does the MiG only work on TTL parts?
> -Kevin

MIG creates a wrapper for the memory code. You don't need to
route the reset input to a pin of the FPGA. Most designs just
use a simple startup circuit (a few flip-flops initialized
to 1 during config in a shift-register configuration) unless
the FPGA needs to wait for some external event to start up.
From: ben on 21 Apr 2008 20:01
>
>MIG creates a wrapper for the memory code. You don't need to
>route the reset input to a pin of the FPGA. Most designs just
>use a simple startup circuit (a few flip-flops initialized
>to 1 during config in a shift-register configuration) unless
>the FPGA needs to wait for some external event to start up.

What you say makes sense and seems to agree with the signal
description in the MIG User Guide. I'm still curious as to why MIG
assigned the signal to an FPGA I/O pin. Maybe there was some option I
got wrong when running MIG.

Thanks for your response!
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