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From: ben on 18 Apr 2008 23:32
I used the latest version of MIG to generate pinouts for a Virtex 4
DDR2 interface. In addition to all the usual Address, Data, and
Control I/Os, MIG assigned an I/O pin for a signal called
SYS_RESET_IN_N. What is the function of this pin?
From: Jim Wu on 21 Apr 2008 06:47
On Apr 18, 11:32 pm, b...(a)hometoolong.inv wrote:
> I used the latest version of MIG to generate pinouts for a Virtex 4
> DDR2 interface. In addition to all the usual Address, Data, and
> Control I/Os, MIG assigned an I/O pin for a signal called
> SYS_RESET_IN_N. What is the function of this pin?

At the risk of stating the obvious, it is a reset pin.

Cheers,
Jim
http://home.comcast.net/%7Ejimwu88/tools/


From: ben on 21 Apr 2008 07:56
But why is it necessary? Doesn't the normal FPGA configuration process
reset the DDR2 interface? I can't find any info on how to use this
input.
From: Mike Harrison on 21 Apr 2008 08:42
On Mon, 21 Apr 2008 04:56:57 -0700, ben(a)hometoolong.inv wrote:

>But why is it necessary? Doesn't the normal FPGA configuration process
>reset the DDR2 interface? I can't find any info on how to use this
>input.

The DDR memory itself will likely require an initialisation sequence - this is certainly the case
for SDRAM - I would imagine this signal tells the controller to perfom this initialisation.
From: Kevin Neilson on 21 Apr 2008 16:09
Jim Wu wrote:
> On Apr 18, 11:32 pm, b...(a)hometoolong.inv wrote:
>> I used the latest version of MIG to generate pinouts for a Virtex 4
>> DDR2 interface. In addition to all the usual Address, Data, and
>> Control I/Os, MIG assigned an I/O pin for a signal called
>> SYS_RESET_IN_N. What is the function of this pin?
>
This is off-topic, but the "_N" probably indicates that this is an
active-low signal; I want to know why we still have new designs with
active-low signals. Is it 1982? Does the MiG only work on TTL parts?
-Kevin
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