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From: giorgos.puiklis on 11 Apr 2008 05:37
Hello,
when trying to synthesize a VHDL file (part of a design) that has
already been compiled and simulated by Modelsim,
ISE gives the following error:

" ERROR:HDLParsers:3524 - "G:/des1/chsam_struct.vhd" Line 132.
Unexpected end of line. "

It refers to the last line of the following code, any idea what this
is..? It is a rather simple code I can't understand what is the
problem :

-----------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY DgChSamplRep IS
PORT(
MClk : IN std_logic;
R : IN std_logic_vector (1 DOWNTO 0);
Rst : IN std_logic;
SerIn : IN std_logic;
Shift_En : IN std_logic;
DO : OUT std_logic_vector (7 DOWNTO 0) BUS;
DgChVal : OUT std_logic_vector (15 DOWNTO 0)
);

-- Declarations

END DgChSamplRep ;

--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ARCHITECTURE struct OF DgChSamplRep IS

-- Architecture declarations

-- Internal signal declarations
SIGNAL ClkInv : std_logic;
SIGNAL ClkInv_En : std_logic;

-- Implicit buffer signal declarations
SIGNAL DgChVal_internal : std_logic_vector (15 DOWNTO 0);

-- Component Declarations
COMPONENT ShiftReg16b
PORT (
Clk : IN std_logic ;
Rst : IN std_logic ;
SerIn : IN std_logic ;
Q : OUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT Tristate8b_exp
PORT (
I0 : IN std_logic ;
I1 : IN std_logic ;
I2 : IN std_logic ;
I3 : IN std_logic ;
I4 : IN std_logic ;
I5 : IN std_logic ;
I6 : IN std_logic ;
I7 : IN std_logic ;
R : IN std_logic ;
O : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;

BEGIN

ClkInv_En <= ClkInv AND Shift_En;

ClkInv <= NOT(MClk);

-- Instance port mappings.
U_0 : ShiftReg16b
PORT MAP (
Clk => ClkInv_En,
Rst => Rst,
SerIn => SerIn,
Q => DgChVal_internal
);
U_2 : Tristate8b_exp
PORT MAP (
I0 => DgChVal_internal(7),
I1 => DgChVal_internal(6),
I2 => DgChVal_internal(5),
I3 => DgChVal_internal(4),
I4 => DgChVal_internal(3),
I5 => DgChVal_internal(2),
I6 => DgChVal_internal(1),
I7 => DgChVal_internal(0),
R => R(0),
O => DO
);
U_3 : Tristate8b_exp
PORT MAP (
I0 => DgChVal_internal(15),
I1 => DgChVal_internal(14),
I2 => DgChVal_internal(13),
I3 => DgChVal_internal(12),
I4 => DgChVal_internal(11),
I5 => DgChVal_internal(10),
I6 => DgChVal_internal(9),
I7 => DgChVal_internal(8),
R => R(1),
O => DO
);

DgChVal <= DgChVal_internal;

END struct;
----------------------------------------------------------------------

Thank you in advance!
Regards,
George
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