case statements- verilog to vhdl
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From: Mike Treseler on 14 Apr 2008 16:01 FP wrote: > From design point of view I am not sure if I should be putting them in > 2 seperate process statements. No. One verilog block is one vhdl process. > My question is > 1) Is the VHDL equivalent of the above, 2 case statements in one > process or 2 different processes with 1 case each? one process > 2) The above is similar to an FSM. One case statement is executing the > present command, while the other is completing the last command. Any > idea on how this should be converted to VHDL? Did the verilog version work? -- Mike Treseler
From: FP on 14 Apr 2008 19:01 On Apr 14, 4:01 pm, Mike Treseler <mike_trese...(a)comcast.net> wrote: > FP wrote: > > From design point of view I am not sure if I should be putting them in > > 2 seperate process statements. > > No. One verilog block is one vhdl process. > > > My question is > > 1) Is the VHDL equivalent of the above, 2 case statements in one > > process or 2 different processes with 1 case each? > > one process > > > 2) The above is similar to an FSM. One case statement is executing the > > present command, while the other is completing the last command. Any > > idea on how this should be converted to VHDL? > > Did the verilog version work? > > -- Mike Treseler The verilog code works but I havent deisnged it. So, I am not sure how its implementation in VHDL woould be.
From: Mike Treseler on 14 Apr 2008 19:20
FP wrote: > The verilog code works but I havent deisnged it. So, I am not sure how > its implementation in VHDL woould be. Unless you post the code, neither am I. -- Mike Treseler |