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From: Lathe_Biosas on 2 Sep 2005 15:43
Hi

After searching more than 3 hours the web, awincupl.exe was found to
compile some CUPL code.
Personally I find it to bugy, so if there is any better suite to get a
..jed file I would appreciate the information.

The programm for a g16v8 needs to have 1 input to decode 8 outputs,
unfortunatelly the code attached does not give the right output
signals. That is, when 0 give as output 00100000 when 1 give as outs a
01000100;

The code was loaded to 2 GALs and the do exactly the same errors. I
tried diferent programmers with the same results.

Could someone please tell me what I'm doing wrong?
Best Regards and Thank you


Code:


Name IO ;
PartNo 00 ;
Date 9/2/2005 ;
Revision 01 ;
Designer Engineer ;
Company None ;
Assembly None ;
Location ;
Device g16v8 ;


/* *************** INPUT PINS *********************/
/* PIN 1 = CLK; */
PIN 1 = IN;

/* *************** OUTPUT PINS *********************/
PIN 19 = !ADR6 ; /* */
PIN 18 = !ADR5 ; /* */
PIN 17 = !ADR4 ; /* */
PIN 16 = !ADR3 ; /* */
PIN 15 = !ADR2 ; /* */
PIN 14 = !WR ; /* */
PIN 13 = !RD ; /* */
PIN 12 = !SEL ; /* */
/*
* Logic: examples of simple gates expressed in CUPL
*/

FIELD input = [IN];
FIELD output = [!SEL, !RD, !WR, !ADR2, !ADR3, !ADR4, !ADR5, !ADR6];

TABLE input => output{
0 => 'b'00100000;
1 => 'b'01000100;
}

From: Jim Granville on 2 Sep 2005 16:47
Lathe_Biosas wrote:

> Hi
>
> After searching more than 3 hours the web, awincupl.exe was found to
> compile some CUPL code.
> Personally I find it to bugy, so if there is any better suite to get a
> .jed file I would appreciate the information.
>
> The programm for a g16v8 needs to have 1 input to decode 8 outputs,
> unfortunatelly the code attached does not give the right output
> signals. That is, when 0 give as output 00100000 when 1 give as outs a
> 01000100;
>
> The code was loaded to 2 GALs and the do exactly the same errors. I
> tried diferent programmers with the same results.
>
> Could someone please tell me what I'm doing wrong?
> Best Regards and Thank you

CUPL creates a .DOC report file - have a look in that, and check the
final reduced equations ARE what you expected.
CUPL can also create/append test vectors, so you can verify operation
on the device programmer.

-jg



> Code:
>
>
> Name IO ;
> PartNo 00 ;
> Date 9/2/2005 ;
> Revision 01 ;
> Designer Engineer ;
> Company None ;
> Assembly None ;
> Location ;
> Device g16v8 ;
>
>
> /* *************** INPUT PINS *********************/
> /* PIN 1 = CLK; */
> PIN 1 = IN;
>
> /* *************** OUTPUT PINS *********************/
> PIN 19 = !ADR6 ; /* */
> PIN 18 = !ADR5 ; /* */
> PIN 17 = !ADR4 ; /* */
> PIN 16 = !ADR3 ; /* */
> PIN 15 = !ADR2 ; /* */
> PIN 14 = !WR ; /* */
> PIN 13 = !RD ; /* */
> PIN 12 = !SEL ; /* */
> /*
> * Logic: examples of simple gates expressed in CUPL
> */
>
> FIELD input = [IN];
> FIELD output = [!SEL, !RD, !WR, !ADR2, !ADR3, !ADR4, !ADR5, !ADR6];
>
> TABLE input => output{
> 0 => 'b'00100000;
> 1 => 'b'01000100;
> }
>

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