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From: chivak on 24 Jun 2008 22:04

Hi ,

Can anyone give me pointers on how to do a gate count estimation for
hardware design in an ASIC.

Do we always have to take the libraries used for an approximate gate
count?

Thanx,
Chivak


From: Darol Klawetter on 24 Jun 2008 22:31
On Jun 24, 9:04 pm, "chivak" <cd_pra...(a)hotmail.com> wrote:
> Hi ,
>
> Can anyone give me pointers on how to do a gate count estimation for
> hardware design in an ASIC.
>
> Do we always have to take the libraries used for an approximate gate
> count?
>
> Thanx,
> Chivak

This is off-topic on a DSP group, nonetheless:

A "gate" has been traditionally defined as a 2-input NAND gate. You
use the equivalent NAND-gate count for each standard logic cell. For
example, I remember that a D flip-flop standard cell (with enable and
reset) equates to about 12 NAND gates. Thus the ASIC standard cell
count will be less that the stated gate count. I'm familiar with one
synchronous design that was 120K standard cells, which translated into
roughly 800K "gates," though the ratio is design-dependent of course.

Darol Klawetter
From: glen herrmannsfeldt on 25 Jun 2008 14:08
chivak wrote:

> Can anyone give me pointers on how to do a gate count
> estimation for hardware design in an ASIC.

As far as I know, for CMOS it is 1/4 the transistor count,
a 2 input NAND using four transistors.

> Do we always have to take the libraries used for
> an approximate gate count?

I believe that there aren't that many ways to do it
in CMOS, so one library is (approximately) as good
as another.

There is some question about the count for buffers using
larger than usual transistors. You might want to increase
the count for them, but that is your choice.

-- glen

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