how to open include file in system generator
in [Embedded]
|
From: krunal on 6 May 2008 09:28 hello........ I have one code in verilog for sigma delta ADC. In ISE it works well but when I want to open in system generator it not works.....I have included one DAC.V in ADC.V file.......so I give whole path of that file. So anyone can help to how to open include file in system generator in black box?????
|
Pages: 1 Prev: Power Quicc 3 problem HW/SW ?? Next: PMOS in parallel with NMOS |