not inferred RAM, on QII
in [FPGA]
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From: LC on 21 Apr 2008 08:41 Hi, On some pretty obvious piece of VHDL (below) QuartusII does not inferred any RAM !!!!!! (whatever "width" value is...) Any help how to convince QII to use RAM and not LEs ??? (all ram options are set to ON... and I've seen it working well on other occasions so what Is wrong here ?) many tks. lc. (I used QII7.0web ed.) --snip-- type k_ram_type is array (0 to (2**width)-1) of std_logic_vector(17 downto 0); shared variable k_ram: k_ram_type; begin process(a_clk) begin if rising_edge(a_clk) then if en_A='1' then if wr_en_A='1' then data_A_out <= k_ram(conv_integer(a_adr)); k_ram(conv_integer(a_adr)) := data_A_in; else data_A_out <= k_ram(conv_integer(a_adr)); end if; end if; end if; end process; --snip--
From: ALuPin on 21 Apr 2008 10:02 Are you sure that Quartus supports shared variables for RAM insertion ?
From: LC on 21 Apr 2008 10:28 Not sure, but if I use a regular variable instead the problem remains the same. No RAM inserted, only LE's lc ALuPin(a)web.de wrote: > Are you sure that Quartus supports shared variables for RAM insertion ?
From: KJ on 21 Apr 2008 11:30 On Apr 21, 8:41 am, LC <cupidoREM...(a)mail.ua.pt> wrote: > Hi, > > On some pretty obvious piece of VHDL (below) > QuartusII does not inferred any RAM !!!!!! > (whatever "width" value is...) > You didn't quite follow the template for inferring memory. > Any help how to convince QII to use > RAM and not LEs ??? > (all ram options are set to ON... > and I've seen it working well on other occasions > so what Is wrong here ?) > > many tks. > > lc. > > (I used QII7.0web ed.) > --snip-- > > type k_ram_type is array (0 to (2**width)-1) > of std_logic_vector(17 downto 0); > shared variable k_ram: k_ram_type; > > begin > > process(a_clk) > begin > if rising_edge(a_clk) then > if en_A='1' then > if wr_en_A='1' then > data_A_out <= k_ram(conv_integer(a_adr)); > k_ram(conv_integer(a_adr)) := data_A_in; > else > data_A_out <= k_ram(conv_integer(a_adr)); > end if; > end if; > end if; > end process; > > --snip-- Remove the "if en_A='1' then " and the corresponding "end if". You can't have a clock enable on the 'read' side. Refer back to the Quartus documentation for the supported templates that infer memory. Kevin Jennings
From: LC on 21 Apr 2008 22:02
Indeed some deviation from the recommended. corrected now. Main culprit was however QII requires a "signal" "variables" won't infer memory ! few more tweaks and is working. tks. lc KJ wrote: > On Apr 21, 8:41 am, LC <cupidoREM...(a)mail.ua.pt> wrote: >> Hi, >> >> On some pretty obvious piece of VHDL (below) >> QuartusII does not inferred any RAM !!!!!! >> (whatever "width" value is...) >> > > You didn't quite follow the template for inferring memory. > >> Any help how to convince QII to use >> RAM and not LEs ??? >> (all ram options are set to ON... >> and I've seen it working well on other occasions >> so what Is wrong here ?) >> >> many tks. >> >> lc. >> >> (I used QII7.0web ed.) >> --snip-- >> >> type k_ram_type is array (0 to (2**width)-1) >> of std_logic_vector(17 downto 0); >> shared variable k_ram: k_ram_type; >> >> begin >> >> process(a_clk) >> begin >> if rising_edge(a_clk) then >> if en_A='1' then >> if wr_en_A='1' then >> data_A_out <= k_ram(conv_integer(a_adr)); >> k_ram(conv_integer(a_adr)) := data_A_in; >> else >> data_A_out <= k_ram(conv_integer(a_adr)); >> end if; >> end if; >> end if; >> end process; >> >> --snip-- > > Remove the "if en_A='1' then " and the corresponding "end if". You > can't have a clock enable on the 'read' side. Refer back to the > Quartus documentation for the supported templates that infer memory. > > Kevin Jennings |