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From: Fei Liu on 5 Apr 2008 21:17
The following code runs well in simulation mode but synthesis fails.
Please let me know how I can get this synthesized, thanks!

Fei
`timescale 1ns / 1ps
module blink_led(clk, d, led);
input clk;
input d;
output wire led;

parameter blink_freq = 2;
reg [blink_freq:0] count = 0;
reg [1:0] state = 0;
reg [1:0] next_state = 0;
assign led = !count[blink_freq];

always @(posedge clk)
begin
state <= next_state;
if(state == 2'b01)
begin
count <= count + 1;
if(count[blink_freq])
next_state <= 2'b10;
else
next_state <= 2'b01;
end
end

always @(state or d) begin
case(state)
2'b00:
if(d)
next_state <= 2'b01;
else
next_state <= 2'b00;
2'b01:
begin
count <= count + 1;
if(count[blink_freq])
next_state <= 2'b10;
else
next_state <= 2'b01;
end
2'b10:
begin
count <= 0;
next_state <= 2'b00;
end
default:
begin
next_state <= state;
end
endcase
end

endmodule

module stimuli;

reg clk=0;
reg d=0;
wire led;

blink_led bl(.clk (clk), .d(d), .led(led));

initial
forever #20 clk = ~clk;

initial begin
#80 d = 1;
#40 d = 0;
#140 d = 1;
forever #40 d = ~d;
end

endmodule

ERROR:Xst:528 - Multi-source in Unit <blink_led> on signal
<Madd_count_addsub0000_cy<0>>
Sources are:
Output signal of LD instance <count_ren_0>
Output signal of FDE instance <count_0>

ERROR:Xst:528 - Multi-source in Unit <blink_led> on signal
<Madd_count_addsub00002>
Sources are:
Output signal of LD instance <count_ren_1>
Output signal of FDE instance <count_1>

ERROR:Xst:528 - Multi-source in Unit <blink_led> on signal
<Madd_count_addsub00004>
Sources are:
Output signal of LD instance <count_ren_2>
Output signal of FDE instance <count_2>
CPU : 6.41 / 6.66 s | Elapsed : 7.00 / 7.00 s

-->

Total memory usage is 154044 kilobytes

Number of errors : 3 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 1 ( 0 filtered)


Process "Synthesize" failed
From: Fei Liu on 5 Apr 2008 22:39
On Apr 5, 9:17 pm, Fei Liu <fei....(a)gmail.com> wrote:
> The following code runs well in simulation mode but synthesis fails.
> Please let me know how I can get this synthesized, thanks!
>
> Fei

I've managed to code this to get synthesis done but I don't understand
why next_state can be assigned in both always blocks but count cannot?
The only difference is count update depends on count itself...

`timescale 1ns / 1ps

module blink_led(clk, d, led);
input clk;
input d;
output wire led;

parameter blink_freq = 2;
reg [blink_freq:0] count = 0;
reg [1:0] state = 0;
reg [1:0] next_state = 0;
assign led = !count[blink_freq];

always @(posedge clk)
begin
state <= next_state;
case(state)
2'b01:
begin
count <= count + 1;
if(count[blink_freq])
next_state <= 2'b10;
else
next_state <= 2'b01;
end
2'b10:
count <= 0;
endcase
end

always @(state or d or count) begin
case(state)
2'b00:
if(d)
next_state <= 2'b01;
else
next_state <= 2'b00;
2'b01:
begin
if(count[blink_freq])
next_state <= 2'b10;
else
next_state <= 2'b01;
end
2'b10:
begin
next_state <= 2'b00;
end
default:
begin
next_state <= state;
end
endcase
end

endmodule

module stimuli;

reg clk=0;
reg d=0;
wire led;

blink_led bl(.clk (clk), .d(d), .led(led));

initial
forever #20 clk = ~clk;

initial begin
#80 d = 1;
#40 d = 0;
#140 d = 1;
forever #40 d = ~d;
end

endmodule
From: glen herrmannsfeldt on 5 Apr 2008 22:52
Fei Liu wrote:

> The following code runs well in simulation mode but synthesis fails.
> Please let me know how I can get this synthesized, thanks!

(snip)

> blink_led bl(.clk (clk), .d(d), .led(led));
>
> initial
> forever #20 clk = ~clk;
>
> initial begin
> #80 d = 1;
> #40 d = 0;
> #140 d = 1;
> forever #40 d = ~d;
> end

It is usual not to be able to synthesize the above logic.
Pretty much anything with a numeric delay won't synthesize.

> ERROR:Xst:528 - Multi-source in Unit <blink_led> on signal
> <Madd_count_addsub0000_cy<0>>
> Sources are:
> Output signal of LD instance <count_ren_0>
> Output signal of FDE instance <count_0>

This means there are two outputs connected together.

You can't do that in real logic as the output drivers
will fight each other, often with large currents flowing.

Without going all the way through the logic, I believe
it is count that has more than one source.

-- glen

From: Muzaffer Kal on 6 Apr 2008 00:01
On Sat, 5 Apr 2008 18:17:24 -0700 (PDT), Fei Liu <fei.liu(a)gmail.com>
wrote:

>The following code runs well in simulation mode but synthesis fails.
>Please let me know how I can get this synthesized, thanks!

I'm assuming you're not trying to synthesize your test-bench ie module
stimuli. You can only synthesize blink_led and if you want to exercise
it after synthesis, you can use the gate level version under your
test-bench or implement in an fpga and drive the pins on the board.

As to synthesizing the blink_led module, you need to make sure that
any signal is driven from only one always block. Put all next_state
and count assignments to the second (combinational) block. You can add
another set of wires for something like count_d and assign it in the
second block (ie count_d = count + 1; etc) and add count <= count_d;
to your first (sequential) block unconditionally.
Your code should look as follows:

always @(posedge clk)
begin
state <= next_state;
count <= count_d;
end

always @(*)
begin
case (state)
...
next_state = foo;
count_d = count + 1;
...
end

Muzaffer Kal
ASIC/FPGA Design Services
DSPIA INC.
http://www.dspia.com
From: Fei Liu on 6 Apr 2008 00:35
On Apr 6, 12:01 am, Muzaffer Kal <k...(a)dspia.com> wrote:
> On Sat, 5 Apr 2008 18:17:24 -0700 (PDT), Fei Liu <fei....(a)gmail.com>
> wrote:
>
> >The following code runs well in simulation mode but synthesis fails.
> >Please let me know how I can get this synthesized, thanks!
>
> I'm assuming you're not trying to synthesize your test-bench ie module
> stimuli. You can only synthesize blink_led and if you want to exercise
> it after synthesis, you can use the gate level version under your
> test-bench or implement in an fpga and drive the pins on the board.
>
> As to synthesizing the blink_led module, you need to make sure that
> any signal is driven from only one always block. Put all next_state
> and count assignments to the second (combinational) block. You can add
> another set of wires for something like count_d and assign it in the
> second block (ie count_d = count + 1; etc) and add count <= count_d;
> to your first (sequential) block unconditionally.
> Your code should look as follows:
>
> always @(posedge clk)
> begin
> state <= next_state;
> count <= count_d;
> end
>
> always @(*)
> begin
> case (state)
> ...
> next_state = foo;
> count_d = count + 1;
> ...
> end
>
> Muzaffer Kal
> ASIC/FPGA Design Services
> DSPIA INC.http://www.dspia.com

Thanks, I think my second iteration does exactly what you described
here. I do have one last doubt about timing. In my synthesizable
version, when I run the test bench, the value of state always lags
behind next_state for 1 or half clock period. My understanding is that
since they are in separate always blocks, the simulation is free to do
this assignment with a delay. Is there a deeper reason why state value
always lag behind next_state for 1 clk?

clk period = 40

0 clk = 0, d = 0, led = 0, state = 00, next_state =
00
20 clk = 1, d = 0, led = 0, state = 00, next_state =
00
40 clk = 0, d = 0, led = 0, state = 00, next_state =
00
60 clk = 1, d = 0, led = 0, state = 00, next_state =
00
80 clk = 0, d = 1, led = 0, state = 00, next_state =
01 <---
100 clk = 1, d = 1, led = 1, state = 01, next_state =
01 <---
120 clk = 0, d = 0, led = 1, state = 01, next_state =
01
140 clk = 1, d = 0, led = 1, state = 01, next_state =
01
160 clk = 0, d = 0, led = 1, state = 01, next_state =
01
180 clk = 1, d = 0, led = 1, state = 01, next_state =
01
200 clk = 0, d = 0, led = 1, state = 01, next_state =
01
220 clk = 1, d = 0, led = 1, state = 01, next_state =
01
240 clk = 0, d = 0, led = 1, state = 01, next_state =
01 <---
260 clk = 1, d = 1, led = 1, state = 01, next_state =
10 <---
280 clk = 0, d = 1, led = 1, state = 01, next_state =
10
300 clk = 1, d = 0, led = 0, state = 10, next_state =
00
320 clk = 0, d = 0, led = 0, state = 10, next_state =
00
340 clk = 1, d = 0, led = 0, state = 00, next_state =
00
360 clk = 0, d = 0, led = 0, state = 00, next_state =
00
380 clk = 1, d = 0, led = 0, state = 00, next_state =
00
400 clk = 0, d = 1, led = 0, state = 00, next_state =
01
420 clk = 1, d = 1, led = 1, state = 01, next_state =
01
440 clk = 0, d = 0, led = 1, state = 01, next_state =
01
460 clk = 1, d = 0, led = 1, state = 01, next_state =
01
480 clk = 0, d = 0, led = 1, state = 01, next_state =
01
500 clk = 1, d = 0, led = 1, state = 01, next_state =
01
520 clk = 0, d = 0, led = 1, state = 01, next_state =
01
540 clk = 1, d = 0, led = 1, state = 01, next_state =
01
560 clk = 0, d = 0, led = 1, state = 01, next_state =
01
580 clk = 1, d = 0, led = 1, state = 01, next_state =
10 <----
600 clk = 0, d = 0, led = 1, state = 01, next_state =
10
620 clk = 1, d = 0, led = 0, state = 10, next_state =
00 <----
640 clk = 0, d = 0, led = 0, state = 10, next_state =
00
660 clk = 1, d = 0, led = 0, state = 00, next_state =
00
680 clk = 0, d = 0, led = 0, state = 00, next_state =
00
700 clk = 1, d = 0, led = 0, state = 00, next_state =
00
720 clk = 0, d = 0, led = 0, state = 00, next_state =
00
740 clk = 1, d = 0, led = 0, state = 00, next_state =
00
760 clk = 0, d = 0, led = 0, state = 00, next_state =
00
780 clk = 1, d = 0, led = 0, state = 00, next_state =
00
800 clk = 0, d = 0, led = 0, state = 00, next_state =
00
820 clk = 1, d = 0, led = 0, state = 00, next_state =
00
840 clk = 0, d = 0, led = 0, state = 00, next_state =
00
860 clk = 1, d = 0, led = 0, state = 00, next_state =
00
880 clk = 0, d = 0, led = 0, state = 00, next_state =
00
900 clk = 1, d = 0, led = 0, state = 00, next_state =
00
920 clk = 0, d = 0, led = 0, state = 00, next_state =
00
940 clk = 1, d = 0, led = 0, state = 00, next_state =
00
960 clk = 0, d = 0, led = 0, state = 00, next_state =
00
980 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1000 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1020 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1040 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1060 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1080 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1100 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1120 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1140 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1160 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1180 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1200 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1220 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1240 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1260 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1280 clk = 0, d = 0, led = 0, state = 00, next_state =
00
1300 clk = 1, d = 0, led = 0, state = 00, next_state =
00
1320 clk = 0, d = 0, led = 0, state = 00, next_state =
00

Also of course I wasn't trying to synthesize the test bench code...

Thanks,
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