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From: FPGA on 31 Mar 2008 12:23
On Mar 29, 12:18 am, John_H <newsgr...(a)johnhandwork.com> wrote:
> Kevin Neilson wrote:
> > mk wrote:
> >> On Fri, 28 Mar 2008 11:14:23 -0700 (PDT), FPGA
> >> <FPGA.unkn...(a)gmail.com> wrote:
>
> >>> what does the following code do
> >>> output <= input[x*(y)-1 -: y];
>
> >> That's called an indexed part select. The first expression signifies
> >> base and the second expression signifies width. It the sign is + it's
> >> an ascending select if it's negative it's a descending select. Your
> >> example is equivalent to input[x*(y)-1: x*(y)-y] ie you need to
> >> subtract (y-1) from the base to get the lower index.
>
> > I think your equivalent should be:  input[x*(y)-1: x*(y)-y+1]
>
> > If I remember correctly, the width has to be a constant.  In this case
> > that would mean y could be a parameter, but not an integer or register.
> > -Kevin
>
> The y that follows the indexed part select operator is the width.  The
> vector mk showed has a width of y bits which is accurate.  The vector
> Kevin showed has a width of y-1 bits which is inaccurate.  Use mk's
> suggestion.
>
> Oh, and invest in a Verilog-2001 reference.
>
> Also - I removed the cross-post to comp.lang.vhdl because this is
> VERILOG!  The VHDL abbreviations doesn't mean "Verilog Hardware
> Description Language."  You can go to comp.lang.verilog for Verilog issues.
>
> - John_H- Hide quoted text -
>
> - Show quoted text -

Thanks always for your valuable help.
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