synchronous reset problems on FPGA
in [FPGA]
|
Prev: how we can prove that really the AES 256 is used to crypt the Bitstream in virtex 5
Next: Problem writing quadrature decoder
From: chrisdekoh on 20 Apr 2008 10:58 Hi, I am wondering if anyone of you have experienced this before. Here goes the reset problem I am facing now. asynchronous reset in FPGAs are usually a big NO-NO. from the articles I am reading, the async reset, normally results in more logic being used to stitch up LUTs together. However, the design I am currently working on requires only one of the blocks to run at 1/4 that of the original clock speed. I am using a DCM to clock divide the master clock, and the output goes into this block. The problem happens when - the reset signal which resets the DCM, is the same reset which goes into this same block. - This will result in a problem, as the clock-divide-by-4 as I call it, will not emit a clock pulse in reset state, as the DCM has not locked yet. the synchronous reset will thus not work for this block. 1) Any ideas of how to circumvent this problem? I would like to use synchronous resets, but also use the divide by 4 clock for the block. 2) Are my concepts of synchronous resets correct? that synchronous resets on FPGA are better than asynchronous resets? thanks Chris
From: Mike Treseler on 20 Apr 2008 12:29 chrisdekoh(a)gmail.com wrote: > Hi, > I am wondering if anyone of you have experienced this before. Here > goes the reset problem I am facing now. asynchronous reset in FPGAs > are usually a big NO-NO. from the articles I am reading, the async > reset, normally results in more logic being used to stitch up LUTs > together. I prefer an asynch assert for simulation of the 'no clock running' case. I generate an asynch assert and sync de-assert reset strobe, something like this. http://home.comcast.net/~mike_treseler/reset.vhd http://home.comcast.net/~mike_treseler/reset.pdf It's just a two flop shifter, reset_out is preset with reset_in. A zero is clocked out to de-assert reset_out. > However, the design I am currently working on requires only one of > the blocks to run at 1/4 that of the original clock speed. I am using > a DCM to clock divide the master clock, and the output goes into this > block. I would clock all the flops at the original clock speed, reset everything the same way, and use clock enable strobes for the slower update rates. -- Mike Treseler
From: chrisdekoh on 20 Apr 2008 21:30 Hi Mike, > > However, the design I am currently working on requires only one of > > the blocks to run at 1/4 that of the original clock speed. I am using > > a DCM to clock divide the master clock, and the output goes into this > > block. > > I would clock all the flops at the original clock speed, > reset everything the same way, and use > clock enable strobes for the slower update rates. > > -- Mike Treseler thanks for your input. When you mean clock enable strobe, do you mean... the following? process (clk) if clk=1 and clk'event then if res = '1' else if clock_enable = '1' end if; end if; end if; --then clock_enable will be in my case asserted one in every 4 clocks to achieve a f/4 MHz kind of data rate... If my understanding is correct, then I have another question. The maximum synthesizable frequency of a core used in the design cannot run at clock speed and only at 1/4 clock speed. currently, I have thus 2 clock domains in this design 1) 1 clock runnning at f MHz 2) 1 clock running at f/4 frequency. I have prevented potential clock domain crossing problems by piping data already into an async FIFO (data entering the design written into the FIFO at f MHz, data read out at f/4 MHz which goes into the core also clocked at f/4 MHz). Since you advised to use the strobe method as I understood above, then how do i go about clocking the core that can run at only f/4 MHz max and still not run into the reset problem stated above? thanks again for your help. Chris
From: Peter Alfke on 20 Apr 2008 21:36 On Apr 20, 6:30 pm, chrisde...(a)gmail.com wrote: > Hi Mike, > > > > However, the design I am currently working on requires only one of > > > the blocks to run at 1/4 that of the original clock speed. I am using > > > a DCM to clock divide the master clock, and the output goes into this > > > block. > > > I would clock all the flops at the original clock speed, > > reset everything the same way, and use > > clock enable strobes for the slower update rates. > > > -- Mike Treseler > > thanks for your input. When you mean clock enable strobe, do you > mean... the following? > > process (clk) > if clk=1 and clk'event then > if res = '1' > > else > if clock_enable = '1' > > end if; > end if; > end if; > > --then clock_enable will be in my case asserted one in every 4 clocks > to achieve a f/4 MHz kind of data rate... > > If my understanding is correct, then I have another question. The > maximum synthesizable frequency of a core used in the design cannot > run at clock speed and only at 1/4 clock speed. currently, I have thus > 2 clock domains in this design > > 1) 1 clock runnning at f MHz > 2) 1 clock running at f/4 frequency. > > I have prevented potential clock domain crossing problems by piping > data already into an async FIFO (data entering the design written into > the FIFO at f MHz, data read out at f/4 MHz which goes into the core > also clocked at f/4 MHz). > > Since you advised to use the strobe method as I understood above, then > how do i go about clocking the core that can run at only f/4 MHz max > and still not run into the reset problem stated above? > > thanks again for your help. > Chris If you use a global clock to distribute the fast clock, but us CE to disable each flip-flop for 3 out of 4 clock ticks, then that part of your design really runs at the quarter clock speed. The flip-flops see only every fourth clock tick, therefore your design will work as you expect. Peter Alfke
From: Mike Treseler on 20 Apr 2008 21:54
chrisdekoh(a)gmail.com wrote: > Since you advised to use the strobe method as I understood above, then > how do i go about clocking the core that can run at only f/4 MHz max > and still not run into the reset problem stated above? There is only one clock domain. The reset circuit is separate. See Peter's answer. Post to comp.lang.vhd if you don't figure it out. -- Mike Treseler |