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From: Chris Metcalf on 29 Jun 2010 09:20
This looks fine, thanks.

Acked-by: Chris Metcalf <cmetcalf(a)tilera.com>

On 6/29/2010 3:32 AM, FUJITA Tomonori wrote:
> Let's use the standard L1_CACHE_ALIGN macro instead.
>
> Signed-off-by: FUJITA Tomonori <fujita.tomonori(a)lab.ntt.co.jp>
> ---
> arch/tile/include/asm/cache.h | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
> index c2b7dcf..ee59714 100644
> --- a/arch/tile/include/asm/cache.h
> +++ b/arch/tile/include/asm/cache.h
> @@ -20,7 +20,6 @@
> /* bytes per L1 data cache line */
> #define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
> -#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
>
> /* bytes per L1 instruction cache line */
> #define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()
>

--
Chris Metcalf, Tilera Corp.
http://www.tilera.com

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