From: tip-bot for Andreas Herrmann on
Commit-ID: f01487119dda3d9f58c9729c7361ecc50a61c188
Gitweb: http://git.kernel.org/tip/f01487119dda3d9f58c9729c7361ecc50a61c188
Author: Andreas Herrmann <herrmann.der.user(a)googlemail.com>
AuthorDate: Tue, 27 Apr 2010 12:13:48 +0200
Committer: H. Peter Anvin <hpa(a)linux.intel.com>
CommitDate: Thu, 13 May 2010 16:21:20 -0700

x86, amd: Check X86_FEATURE_OSVW bit before accessing OSVW MSRs

If host CPU is exposed to a guest the OSVW MSRs are not guaranteed
to be present and a GP fault occurs. Thus checking the feature flag is
essential.

Cc: <stable(a)kernel.org> # .32.x .33.x
Signed-off-by: Andreas Herrmann <andreas.herrmann3(a)amd.com>
LKML-Reference: <20100427101348.GC4489(a)alberich.amd.com>
Signed-off-by: H. Peter Anvin <hpa(a)linux.intel.com>
---
arch/x86/kernel/process.c | 12 +++++++-----
1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 28ad9f4..0415c3e 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
* check OSVW bit for CPUs that are not affected
* by erratum #400
*/
- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
- if (val >= 2) {
- rdmsrl(MSR_AMD64_OSVW_STATUS, val);
- if (!(val & BIT(1)))
- goto no_c1e_idle;
+ if (cpu_has(c, X86_FEATURE_OSVW)) {
+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
+ if (val >= 2) {
+ rdmsrl(MSR_AMD64_OSVW_STATUS, val);
+ if (!(val & BIT(1)))
+ goto no_c1e_idle;
+ }
}
return 1;
}
--
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