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From: techG on 22 Jun 2008 12:20
Hi all,
I have a camera and a Virtex-5 FPGA, and i would like to store frames
in FPGA Block Ram.
In my design (that worked with Spartan-3E) i need to double camera
clock frequency, in order to get all data, because camera send data on
both clock edges.
The problem is the following: I can't use DCM, because camera clock
frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
"DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
Mode Range is 1-40 Mhz".
How can I avoid this problem? Do you think that I could use component
DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
Multiplier that works fine?

Giulio
From: Hauke D on 22 Jun 2008 12:47
On Jun 22, 6:20 pm, techG <giuliopul...(a)gmail.com> wrote:
> In my design (that worked with Spartan-3E) i need to double camera
> clock frequency, in order to get all data, because camera send data on
> both clock edges.

Have you looked into DDR flip-flops? Those should allow you to read
data coming in on both clock edges at the regular clock frequency.
Check out the Virtex 5 IDDR input primitive.

Regards,
-- Hauke D
From: Symon on 22 Jun 2008 16:48
techG wrote:
> Hi all,
> I have a camera and a Virtex-5 FPGA, and i would like to store frames
> in FPGA Block Ram.
> In my design (that worked with Spartan-3E) i need to double camera
> clock frequency, in order to get all data, because camera send data on
> both clock edges.
> The problem is the following: I can't use DCM, because camera clock
> frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> Mode Range is 1-40 Mhz".
> How can I avoid this problem? Do you think that I could use component
> DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> Multiplier that works fine?
>
> Giulio

Hi Giulio,
So, your input frequency is 6MHz. The wizard tells you that "DFS Low
Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps
you should use your DCM in DFS Low Frequency Mode.
HTH., Syms.
p.s It's Hz not hz.


From: Peter Alfke on 22 Jun 2008 17:21
On Jun 22, 1:48 pm, "Symon" <symon_bre...(a)hotmail.com> wrote:
> techG wrote:
> > Hi all,
> > I have a camera and a Virtex-5 FPGA, and i would like to store frames
> > in FPGA Block Ram.
> > In my design (that worked with Spartan-3E) i need to double camera
> > clock frequency, in order to get all data, because camera send data on
> > both clock edges.
> > The problem is the following: I can't use DCM, because camera clock
> > frequency is about 163 ns (~6 Mhz), and when I'm trying to generate
> > DCM (selecting Maximum Range Mode) , Xilinx Clock Wizard says that
> > "DLL Low Frequency Mode Range is: 19-32 Mhz, and DFS Low Frequency
> > Mode Range is 1-40 Mhz".
> > How can I avoid this problem? Do you think that I could use component
> > DCM of Unisim Library? Moreover, isn't there a VHDL 2X Clock
> > Multiplier that works fine?
>
> > Giulio
>
> Hi Giulio,
> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps
> you should use your DCM in DFS Low Frequency Mode.
> HTH., Syms.
> p.s It's Hz not hz.

If I remember right (I am at home on this beautiful sunday) the output
frequency then must be above 19 MHz.
So you would have to multiply by 4 and then use a flip-flp to divide
by 2.

The suggested use of the DDR input seems to be best, it gives you two
parallel bits at the 6 MHz frequency. If you prefer 12 MHz, I could
mention "my" frequency doubler from "six easy pieces".

There are several solutions...
Peter Alfke

From: Hauke D on 22 Jun 2008 18:02
On Jun 22, 10:48 pm, "Symon" <symon_bre...(a)hotmail.com> wrote:
> Hi Giulio,
> So, your input frequency is 6MHz. The wizard tells you that "DFS Low
> Frequency Mode Range is 1-40 Mhz". Notice how 6 is between 1 and 40. Perhaps
> you should use your DCM in DFS Low Frequency Mode.
> HTH., Syms.
> p.s It's Hz not hz.

I believe the problem is that the clock doubler is one of the DLL (not
DFS) outputs, where the minimum input frequency, even in low frequency
mode, is 19 MHz.

Regards,
-- Hauke D
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