www.sicortex.com
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From: matt.reilly on 6 Apr 2008 12:49 I'll try to catch up on a few of the questions and conjectures: 1. The SiCortex founders (Jud Leonard, John Mucci, and I) had worked before at Digital (all three), Thinking Machines (John), Symbolics (Jud) and other places. We've since added folks from a lot of different places. (But I can't think of any Apollo alums, though I don't have the whole list of folks at my fingertips.) 2. The DMA engine microcode is published. The brave and willing can certainly use it as a starting place for new approaches. 3. The systems are designed with a focus on reliability, low power, deployability, and good price performance for applications that scale to hundreds or thousands of processors. (We also fit a few other profiles that go beyond this focus, but this is what we were thinking when we designed and built the product.) 4. We implement MPI because that is what the major part of our target markets requires. We do pretty well at it too. The MPI implementation (based on MPICH) talks to the DMA engine through a work-queue based interface. The DMA engine microcode also supports IP over the SiCortex fabric and a high performance communication path to support the Lustre parallel file system.
From: already5chosen on 6 Apr 2008 13:19 Matt, Could you comment on Paul Gotch's speculations above (about MIPS 20Kc) ?
From: Nick Maclaren on 6 Apr 2008 14:17 In article <aa530dfa-c87f-4569-a915-f23fd2be8548(a)k37g2000hsf.googlegroups.com>, matt.reilly(a)sicortex.com writes: |> |> We've since added folks from a lot of different places. (But I can't |> think of any |> Apollo alums, though I don't have the whole list of folks at my |> fingertips.) Ah. My source got it wrong, then. Regards, Nick Maclaren.
From: Chris Thomasson on 9 Apr 2008 00:20 <matt.reilly(a)sicortex.com> wrote in message news:aa530dfa-c87f-4569-a915-f23fd2be8548(a)k37g2000hsf.googlegroups.com... > I'll try to catch up on a few of the questions and conjectures: > > 1. The SiCortex founders (Jud Leonard, John Mucci, and I) had worked > before at > Digital (all three), Thinking Machines (John), Symbolics (Jud) and > other places. > We've since added folks from a lot of different places. (But I can't > think of any > Apollo alums, though I don't have the whole list of folks at my > fingertips.) A flood of talented people simply cannot hurt anyone! :^D > 2. The DMA engine microcode is published. The brave and willing can > certainly > use it as a starting place for new approaches. Perfect. > 3. The systems are designed with a focus on reliability, low power, > deployability, > and good price performance for applications that scale to hundreds or > thousands > of processors. (We also fit a few other profiles that go beyond this > focus, but this > is what we were thinking when we designed and built the product.) IMHO, your systems seem to make a lot of sense. > 4. We implement MPI because that is what the major part of our target > markets > requires. We do pretty well at it too. The MPI implementation (based > on MPICH) > talks to the DMA engine through a work-queue based interface. The DMA > engine > microcode also supports IP over the SiCortex fabric and a high > performance > communication path to support the Lustre parallel file system. What do you think about my initial idea on how to program your systems? That is, using advanced shared-memory multi-threading techniques for intra-node communication, and MPI for inter-node communication... I think it should work very well. I am always interested in being able to create and play around with my own algorithms. I appreciate that your DMA engine microcode is available; have you applied for any patents?
From: matt.reilly on 9 Apr 2008 12:17
On Apr 6, 1:19 pm, already5cho...(a)yahoo.com wrote: > Matt, > Could you comment on Paul Gotch's speculations above (about MIPS > 20Kc) ? We looked at the 20Kc and liked it. However, it was a hard macro (that is, MIPS supplies completed masks, not synthesizable verilog) and designed for 130nm. Our technology target was 90nm. The team had lots of experience in doing design shrinks and felt the cost of shrinking the 20Kc was prohibitive. Further, the 20Kc as it stood was not designed for a cache coherent SMP. Fitting the necessary changes into a hard macro made it even more problematic. We chose the 5Kf, a 64 bit soft IP block from MIPS. Then we worked hard at the synthesis flow to make it run at 500 MHz and stay within a sub-watt power budget. matt |