From: Jeremy Fitzhardinge on
On 03/22/2010 08:20 AM, Colin King wrote:
> "If software clears the PS (page size) bit in a present PDE (page directory
> entry), that will cause linear addresses mapped through this PDE to use
> 4-KByte pages instead of using a large page after old TLB entries are
> invalidated. Due to this erratum, if a code fetch uses this PDE before the
> TLB entry for the large page is invalidated then it may fetch from a different
> physical address than specified by either the old large page translation or
> the new 4-KByte page translation. This erratum may also cause speculative code
> fetches from incorrect addresses."
>

Does this only affect non-PAE 32-bit? Or does it also affect 3 and 4
level pagetables with 2MB large pages?

J
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From: H. Peter Anvin on
On 04/12/2010 01:02 AM, Andi Kleen wrote:
> Colin King <colin.king(a)canonical.com> writes:
>>
>> +static void __init check_atom(void)
>> +{
>> +
>> + /*
>> + * Disable 4MB page tables to work around Intel errata AAE44 for
>> + * Atom. We cannot guarantee stopping undefined processor behaviour
>> + * when two pageing structure translations differ with respect to
>> + * page frame sizes. Hence, for Atoms we disable the PSE.
>> + */
>> + if (boot_cpu_data.x86_model == 0x1c) {
>
> Perhaps someone else pointed that out already, but you obviously
> need to check for x86_vendor == X86_VENDOR_INTEL and x86_family == 6 too,
> otherwise you'll get false positives.
>
> Besides such workarounds are normally in arch/x86/kernel/cpu/intel.c.
> bugs.c is really obsolete.
>

Much more than that, the constraint is clearly not strict enough. I'm
currently trying to work out internally what the actual constraint
should be (it's a bit of a documentation hole at the moment.)

-hpa

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