16:32 far pointers in OpenWatcom C/C++
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From: Jonathan de Boyne Pollard on 30 Mar 2010 22:13 > >> >> Which is why I didn't say "the reason". (-: It's worth thinking about >> whether there now exist many mainstream processor architectures that >> provide flat addressing where instruction set addresses are the same >> width as, or narrower than, the general-purpose data registers, and >> whether processor architectures that are even close to the I=L=P >> model are not overwhelmingly in the minority. It's true for IA64 that >> IS addresses are the same width as data registers (GR0 and IP being >> both 64 bits wide). It's also true for the 68xx and the 680x0 >> architectures, that M. Flass was lamenting, earlier, to be rarities >> these days, and no longer really part of the personal computer >> market. It's certainly not the case for the x86 architecture (48-bit >> CS:EIP being wider than 32-bit EAX). >> > is it possible to use 48-bit CS:EAX for point one big array of > len=3FFF_FFFF_FFFF in one program? > Yes (assuming that you really mean something like DS:ESI), but no operating system that I know of provides an execution environment like that for applications, and the size would be smaller by the number of non-value bits in a selector register, as well as by whatever selectors were needed for other purposes. The pointers would be huge pointers. I don't know off-hand whether OpenWatcom C/C++ supports 16:32 huge pointers. (It and several other compilers support 16:16 huge pointers, of course, as do several operating systems.) The way to overcome the 32-bit limitation of the linear address space, of course, is to remember that before paging on x86 there was segment swapping. One just invalidates all but one of the segments, and swaps segments on demand. (Clever tricks with page tables can ameliorate the huge amount of I/O that this would otherwise involve on every swap.) Again, this requires operating system support that no operating system that I know of provides. But for a freestanding program, such an idea is feasible.
From: io_x on 31 Mar 2010 07:49
"Jonathan de Boyne Pollard" <J.deBoynePollard-newsgroups(a)NTLWorld.COM> ha scritto nel messaggio news:IU.D20100331.T021341.P4234.Q0(a)J.de.Boyne.Pollard.localhost... > > >>> >>> Which is why I didn't say "the reason". (-: It's worth thinking about >>> whether there now exist many mainstream processor architectures that provide >>> flat addressing where instruction set addresses are the same width as, or >>> narrower than, the general-purpose data registers, and whether processor >>> architectures that are even close to the I=L=P model are not overwhelmingly >>> in the minority. It's true for IA64 that IS addresses are the same width as >>> data registers (GR0 and IP being both 64 bits wide). It's also true for the >>> 68xx and the 680x0 architectures, that M. Flass was lamenting, earlier, to >>> be rarities these days, and no longer really part of the personal computer >>> market. It's certainly not the case for the x86 architecture (48-bit CS:EIP >>> being wider than 32-bit EAX). >>> >> is it possible to use 48-bit CS:EAX for point one big array of ^^^^^^ yes i mean DS:EAX >> len=3FFF_FFFF_FFFF in one program? >> > Yes (assuming that you really mean something like DS:ESI), but no |