From: glen herrmannsfeldt on
Jerry Avins <jya(a)ieee.org> wrote:
(snip, I wrote)

>> Hmm. My first thought about distortion is that it should be
>> proportional to the signal, or some low power of the signal,
>> such that it goes to zero as the signal goes to zero.

> Typical distortion is due to nonlinearity. When the nonlinearity is low
> enough to be adequately modeled by a parabola, distortion goes with the
> square of the signal. Operating the system at a point of inflection can
> greatly reduce distortion, but when it does occur, it increases as the
> signal's cube.

Yes, by "low power" I meant square or cube. (Not the usual meaning
of low power in this group.)

-- glen
From: Jerry Avins on
glen herrmannsfeldt wrote:
> Jerry Avins <jya(a)ieee.org> wrote:
> (snip, I wrote)
>
>>> Hmm. My first thought about distortion is that it should be
>>> proportional to the signal, or some low power of the signal,
>>> such that it goes to zero as the signal goes to zero.
>
>> Typical distortion is due to nonlinearity. When the nonlinearity is low
>> enough to be adequately modeled by a parabola, distortion goes with the
>> square of the signal. Operating the system at a point of inflection can
>> greatly reduce distortion, but when it does occur, it increases as the
>> signal's cube.
>
> Yes, by "low power" I meant square or cube. (Not the usual meaning
> of low power in this group.)

A perfectly reasonable use, but I missed it.

Jerry
--
Engineering is the art of making what you want from things you can get.
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From: Eric Jacobsen on
On 11/19/2009 3:31 PM, Randy Yates wrote:
> Eric Jacobsen<eric.jacobsen(a)ieee.org> writes:
>
>> On 11/19/2009 11:02 AM, Randy Yates wrote:
>>> Eric Jacobsen<eric.jacobsen(a)ieee.org> writes:
>>>
>>>> On 11/19/2009 5:22 AM, Randy Yates wrote:
>>>>> "guru_kaliraj"<guru_kaliraj(a)yahoo.com> writes:
>>>>>
>>>>>> Hi Eric,
>>>>>> This explains me clearly why I'm getting less SNR. Yes!. Both sample
>>>>>> rate& signal is not synchronized& hence as you mentioned my signal phase
>>>>>> is playing a role of affecting SNR. Thanks for the reply.
>>>>>> Probably, writing some algorithm so that my sample start& end is
>>>>>> controlled (I'm planning to select samples - to get same value of digital
>>>>>> code at start& end -- and this will make sure that phase drift is
>>>>>> adjusted) will help me to increase the SNR.
>>>>>>
>>>>>> Thanks again!
>>>>> Wow! I'm glad the two of you know what you're talking about. I really
>>>>> don't have a clue.
>>>>>
>>>>> In fact, I ran a Matlab simulation of this and found just the opposite,
>>>>> i.e., that when Fs = 4*f, the measured SNR is way, way bigger than the
>>>>> actual.
>>>>>
>>>>> That's because, when the non-quantization noise is much less than the
>>>>> quantization noise, you're only going to get a repeating sequence of
>>>>> four values, and that looks like a pure sine wave at Fs/4 without ANY
>>>>> (wideband) quantization noise. The quantization noise translates into
>>>>> phase and/or magnitude error of the sine wave.
>>>> Isn't phase and/or magnitude error noise?
>>> Not when you're expecting to be able to measure noise in the non-Fs/4
>>> bins of the FFT.
>> How would you be able to distinguish the difference?
>
> Actually there could be another phenomenom going on here I haven't
> mentioned. When the signal frequency is exactly Fs/4, then any harmonics
> would alias back to either DC or Fs/4. Also, any DC offset is obviously
> going to be at DC.
>
> So what you have is a measurement method that could very possibly only
> show non-zero power in bins 0 and N/4.
>
> And just to clarify, you know I am referring to the situation where you
> get THE EXACT SAME 4 values each cycle, right? Wouldn't you agree that's
> a pure "signal" without any "noise".

The question is how accurately the sampled sequence represents the input
signal, or, more specifically to the OP's original question, how well it
reveals a representative SNR figure for the ADC. If the ADC only has
four output levels, then maybe it's good enough, but in my judgement
such a sequence does a very poor job of characterizing an ADC with more
levels than that.

When one assures that the signal test tone and sample clock are NOT
phase locked, then it's far more likely that more of the quantization
levels will be exercised (hopefully, eventually, all of them). If the
output sequence is analyzed over a window where all or a large fraction
of the output codes are included, then one can do a FAR better job of
characterizing the ADC than if only four output levels are ever tested.

This may mean that a long sequence is needed, and so the output has to
be processed over a large enough window to include enough output codes
to get the desired information.

I didn't interpret the goal as being finding what to do to get the
prettiest FFT output, as you're clearly right that phase-locking the
test signal to the sample clock will do that. I just don't think that's
a good way to exercise the ADC at the high-frequency end for the reasons
I mention above.

It also requires a better understanding of interpreting FFT outputs than
just looking for the highest peak with the lowest non-peak bin energy.

--
Eric Jacobsen
Minister of Algorithms
Abineau Communications
http://www.abineau.com
From: Randy Yates on
Eric Jacobsen <eric.jacobsen(a)ieee.org> writes:

> On 11/19/2009 3:31 PM, Randy Yates wrote:
>> Eric Jacobsen<eric.jacobsen(a)ieee.org> writes:
>>
>>> On 11/19/2009 11:02 AM, Randy Yates wrote:
>>>> Eric Jacobsen<eric.jacobsen(a)ieee.org> writes:
>>>>
>>>>> On 11/19/2009 5:22 AM, Randy Yates wrote:
>>>>>> "guru_kaliraj"<guru_kaliraj(a)yahoo.com> writes:
>>>>>>
>>>>>>> Hi Eric,
>>>>>>> This explains me clearly why I'm getting less SNR. Yes!. Both sample
>>>>>>> rate& signal is not synchronized& hence as you mentioned my signal phase
>>>>>>> is playing a role of affecting SNR. Thanks for the reply.
>>>>>>> Probably, writing some algorithm so that my sample start& end is
>>>>>>> controlled (I'm planning to select samples - to get same value of digital
>>>>>>> code at start& end -- and this will make sure that phase drift is
>>>>>>> adjusted) will help me to increase the SNR.
>>>>>>>
>>>>>>> Thanks again!
>>>>>> Wow! I'm glad the two of you know what you're talking about. I really
>>>>>> don't have a clue.
>>>>>>
>>>>>> In fact, I ran a Matlab simulation of this and found just the opposite,
>>>>>> i.e., that when Fs = 4*f, the measured SNR is way, way bigger than the
>>>>>> actual.
>>>>>>
>>>>>> That's because, when the non-quantization noise is much less than the
>>>>>> quantization noise, you're only going to get a repeating sequence of
>>>>>> four values, and that looks like a pure sine wave at Fs/4 without ANY
>>>>>> (wideband) quantization noise. The quantization noise translates into
>>>>>> phase and/or magnitude error of the sine wave.
>>>>> Isn't phase and/or magnitude error noise?
>>>> Not when you're expecting to be able to measure noise in the non-Fs/4
>>>> bins of the FFT.
>>> How would you be able to distinguish the difference?
>>
>> Actually there could be another phenomenom going on here I haven't
>> mentioned. When the signal frequency is exactly Fs/4, then any harmonics
>> would alias back to either DC or Fs/4. Also, any DC offset is obviously
>> going to be at DC.
>>
>> So what you have is a measurement method that could very possibly only
>> show non-zero power in bins 0 and N/4.
>>
>> And just to clarify, you know I am referring to the situation where you
>> get THE EXACT SAME 4 values each cycle, right? Wouldn't you agree that's
>> a pure "signal" without any "noise".
>
> The question is how accurately the sampled sequence represents the
> input signal, or, more specifically to the OP's original question, how
> well it reveals a representative SNR figure for the ADC. If the ADC
> only has four output levels, then maybe it's good enough, but in my
> judgement such a sequence does a very poor job of characterizing an
> ADC with more levels than that.

I agree completely.

> When one assures that the signal test tone and sample clock are NOT
> phase locked, then it's far more likely that more of the quantization
> levels will be exercised (hopefully, eventually, all of them). If the
> output sequence is analyzed over a window where all or a large
> fraction of the output codes are included, then one can do a FAR
> better job of characterizing the ADC than if only four output levels
> are ever tested.

I agree completely.

> This may mean that a long sequence is needed, and so the output has to
> be processed over a large enough window to include enough output codes
> to get the desired information.
>
> I didn't interpret the goal as being finding what to do to get the
> prettiest FFT output, as you're clearly right that phase-locking the
> test signal to the sample clock will do that. I just don't think
> that's a good way to exercise the ADC at the high-frequency end for
> the reasons I mention above.
>
> It also requires a better understanding of interpreting FFT outputs
> than just looking for the highest peak with the lowest non-peak bin
> energy.

Hey Eric,

I think we are in vigorous agreement! I think somehow we have "passed in
the night".

The thing that confused me in the first couple of posts you made on this
topic is that it seems (perhaps I misinterpreted you) that you were
asserting this scenario would result in a measured SNR that was *worse*
than actual. As I said previously, I found just he opposite: these sorts
of characteristics of the method would result in a measured SNR that was
much higher than the actual.
--
Randy Yates % "So now it's getting late,
Digital Signal Labs % and those who hesitate
mailto://yates(a)ieee.org % got no one..."
http://www.digitalsignallabs.com % 'Waterfall', *Face The Music*, ELO
From: Jerry Avins on
Eric Jacobsen wrote:
> On 11/19/2009 3:31 PM, Randy Yates wrote:

...


>> And just to clarify, you know I am referring to the situation where you
>> get THE EXACT SAME 4 values each cycle, right? Wouldn't you agree that's
>> a pure "signal" without any "noise".
>
> The question is how accurately the sampled sequence represents the input
> signal, or, more specifically to the OP's original question, how well it
> reveals a representative SNR figure for the ADC. If the ADC only has
> four output levels, then maybe it's good enough, but in my judgement
> such a sequence does a very poor job of characterizing an ADC with more
> levels than that.
>
> When one assures that the signal test tone and sample clock are NOT
> phase locked, then it's far more likely that more of the quantization
> levels will be exercised (hopefully, eventually, all of them). If the
> output sequence is analyzed over a window where all or a large fraction
> of the output codes are included, then one can do a FAR better job of
> characterizing the ADC than if only four output levels are ever tested.
>
> This may mean that a long sequence is needed, and so the output has to
> be processed over a large enough window to include enough output codes
> to get the desired information.
>
> I didn't interpret the goal as being finding what to do to get the
> prettiest FFT output, as you're clearly right that phase-locking the
> test signal to the sample clock will do that. I just don't think that's
> a good way to exercise the ADC at the high-frequency end for the reasons
> I mention above.
>
> It also requires a better understanding of interpreting FFT outputs than
> just looking for the highest peak with the lowest non-peak bin energy.

I don't see a disagreement. You address the issue of what the OP needs
to do to get an accurate measurement. Randy addresses the OP's
puzzlement at not getting the measurement he expected. Orthogonal!

Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������