From: dgreig on 26 Jul 2010 04:57
On Jul 26, 8:54 am, dgreig <dgr...(a)ieee.org> wrote:
> On Jul 25, 2:15 am, Rob <noth...(a)nowhere.com> wrote:
> > Hi,
> > Using Altera Model-Sim to do a gate level simulation. The .vo file that
> > is produced doesn't seem to be modeling the internal RAM's correctly. In
> > the design they are instantiated as 12bit but the EDA netlist has them
> > as 4 bits.
> > Any help on this? Has anyone experienced a similar problem?
> > Regards,
> > Rob
> Best to read the memory section of the device datasheet to see why
> it's splitting into 3 x 4 bit blocks. For example a M9k in stratix can
> be split into following during synthesis:
> What your seeing is expected behaviour.
> Best Regards
I should mention that a M9k, for example, can be split into 2 x 4.5k
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