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ANNC: FPGA Design Software Webcast Lattice is holding a webcast today, Wednesday, May 7th, on our latest version of our FPGA software design tools "ispLEVER 7.1 FPGA Design Tool Technical Rollout." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In a... 7 May 2008 14:53
Forking in One-Hot FSMs > You'll also find that changes (like switching the Nobl SRAM to DRAM as an example) can be accomodated without having to change *everything*. That has been on my mind because there is a DRAM on my board. Not only will the DRAM require more cycles but perhaps too a varying number of cycles depending on the seq... 7 May 2008 14:04
ps2 mouse protocol Hi, I'm trying to communicate with the ps2 mouse. So I first force the ps2c line to '0' for 100us. Then I force the ps2d line to '0' and ps2c to high impedance. Now the mouse should take over the ps2c line and send a falling edge on ps2c. But it does not, and ps2c stays '1'. And thus my state machine infinitely ... 7 May 2008 14:04
DSP48 Inference Template for XST I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M (where M=A*B) I can get XST to do any of these, one or two at a time, but when I try to do all at once it adds a bunch of fabric. Any suggestions? The code below, for example, pr... 7 May 2008 12:24
Does anyone have sdio protocol experience? I am trying to write an sdio host controller. sdio is an extension to the sd/mmc protocol used on memory cards. It is used for pda peripheral devices, for example. Note that this question is about the sdio protocol, not the spi protocol that is part of the sdio/sd/mmc specification. I am able to send and ... 7 May 2008 11:35
Call for Papers: International Conference on Computer Science and Applications ICCSA 2008 Call for Papers: International Conference on Computer Science and Applications ICCSA 2008 From: International Association of Engineers (IAENG) San Francisco, USA, 22-24 October, 2008 http://www.iaeng.org/WCECS2008/ICCSA2008.html The conference ICCSA'08 is held under the World Congress on Engineering 2008. The W... 7 May 2008 06:28
Getting started with VHDL and Verilog Hi all, My background is in Software Engineering C,C++,Java and Unix. I am getting started with VHDL and Verilog. What is the good way/books/ websites/training to get started? I have B.S. and M.S. in Computer Engineering. Also, what is the learning curve in VHDL and Verilog? Please let me know. Thanks Jay ... 7 May 2008 04:53
FPGA dev kit with 4-8 Cyclones or Spartans Hello. We need a boards with 4 or 6 or even 8 identical FPGA chips installed, each one should be mid-range Altera Cyclone II or III, let say, each chip should contain between 30.000 LEs and 60.000 LEs. It can be Xilinx Spartan, but board should contain 4-6 or 8 Spartan chips with roughly same logic capacity. Bo... 7 May 2008 03:18
Argh! Need help debugging Xilinx .xsvf Player (XAPP058) On May 6, 11:33 am, "MM" <mb...(a)yahoo.com> wrote: Okay, but I don't know how to do this. Where do I "pick the code" that you refer to? Martin is talking about the source code for the microcontroller... Oh!!! Do you mean this user-supplied function? void waitTime(long microsec); Now we're ... 6 May 2008 22:24
BRAM initialization / bitstream configuration Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the beginning of configurable part ( of bitstream) correspond to BRAM initialization ? * how could i initialize BRAM differently ? Thank you ! M.B ... 6 May 2008 22:24
warning from ISE 9.2 Hi, waht does that mean : Loading device for application Rf_Device from file '3s200.nph' in environment /home/thorsten/Xilinx92i. WARNING:Xst:2677 - Node <b_reg_0> of sequential type is unconnected in block <ps2_rx>. WARNING:Xst:2677 - Node <b_reg_1> of sequential type is unconnected in block <ps2rx>. WARNING... 6 May 2008 22:24
EDK9.2i simulation problems. Hi 1) I am having some EDK simulation problems. I am using EDK9.2i with microblaze 7. I have attached a peripheral to the FSL bus using EDK's configure coprocessor and written its corresponding drivers for the peripheral which has commands like the one below. ie.. #include "mb_interface.h" ..... mi... 6 May 2008 22:24
Aldec Active-HDL 7.3 sp1 [stimulators] On 3 mai, 04:47, 0xdeadbeef <Przemyslaw.D...(a)gmail.com> wrote: Hi all. I'm brand new in fpga subject so please be patient :P My problem is about to use stimulatorin waveform. Well, exactly- there is no such thing as stimulator as it was in ahdl 7.1. How to add it then ? Please help me because w/o it... 6 May 2008 22:24
Style for Highly-Pipelined State Machines KJ wrote: "Kevin Neilson" <kevin_neilson(a)removethiscomcast.net> wrote in message news:fvfm29$on81(a)cnn.xsj.xilinx.com... KJ wrote: "Kevin Neilson" <kevin_neilson(a)removethiscomcast.net> wrote in message news:fv7i38$69n6(a)cnn.xsj.xilinx.com... My question: what is the cleanest way to describe a... 6 May 2008 22:24
Silicon Silicon Wafers at PCASilicon.com PCA supplies silicon wafers for the semiconductor industry. Our products include wafers, thin films and more. We also offer polishing, reclaiming, slicing and lapping of wafers. http://www.ogogo123sina.cn/Silicon.htm ... 6 May 2008 22:24
Looking for FPGA/CPLD skills to develop prototype I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chicago area preferred. cjt101 at yahoo.com ... 6 May 2008 22:24
Xilinx ISE 10 in CentOS not showing in application menu list Hi, This is my first time install Xilinx ISE in CentOS, I thought it's the free clone of RHEL. But I cannot find the ISE in the application menu list. I don't mean I have to have it, but just don't know if it's the default like that. I don't know if it's showing in the RHEL or your CentOS. I am pleased to see ho... 6 May 2008 22:24 |