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CoreTimer programming in Actel SoftConsole Hello, I am trying to measure the execution time of some code using a CoreTimer block connected to a Cortex-M1 processor design in an Actel Fusion part. My problem is that TMR_current_value() always returns 0. I am trying to run in TMR_ONE_SHOT_MODE but I have also tried continuous mode but no change. I ha... 13 Aug 2010 14:39
SPAM Re: Fueling your car with natural gas from home "jt_eaton" <z3qmtr45(a)n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message news:eYednd6r2dXWAoPRnZ2dnUVZ_qadnZ2d(a)giganews.com... this site was doing a great job keeping out the spam. How did this slip through? --------------------------------------- Posted through http://www.FPGARelated.com No o... 13 Aug 2010 14:39
Why is Google so F****** dense about SPAM? "rickman" <gnuarm(a)gmail.com> wrote in message news:c26e6846-bfea-4123-9a2f-9aa2fed77ec3(a)j8g2000yqd.googlegroups.com... Why is Google too dense to fix their SPAM problem? There are so many ways they could address the problem and as far as I can tell, they treat it as a PR concern and have tried to give us ... 13 Aug 2010 14:39
How to use VIO and core inserter at the same time. Hi, I'am seeking a way to use VIO and core inserter at the same time. I found that if I want to use VIO , I must also instantiating ILA. I feel it's awkward. Please help me find a better way.Thanks. --------------------------------------- Posted through http://www.FPGARelated.com ... 13 Aug 2010 17:56
XC5VTX240T-2FF1759I4177 Could someone please help me to identify the suffix, "4177", on this Virtex-5 device and what it calls out as well as the meaning? Could I use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 suffix)? Avnet advertizes them both however the one with the "4177" suffix is roughly $1,000.00 more? It seem... 12 Aug 2010 23:31
Spartan3a: improving DCM performance and Phil, what board are you using? Cant you just swap the oscillator for a faster one? Jon --------------------------------------- Posted through http://www.FPGARelated.com ... 13 Aug 2010 20:08
Altera Sales Does anybody have an email address for Altera Sales in South East Asia ? All email to Altera and their distributors is not being answered. Thanks, rudi ... 12 Aug 2010 01:42
Annual ASIC Prototyping-Verification with FPGA Survey – Free summary and Amazon or Dangdang drawings Hi all. Our annual survey is now open for responses in both English and Chinese. Free survey summary of results and Amazon (or Dangdang) drawings for all who qualify. Deadline for completion is Aug 18th. Cheers. -- John -- Deadline extended to include global inputs -- Welcome to the Third Annual Chip Design ... 11 Aug 2010 14:43
DMA operation to 64-bits PC platform On Jul 6, 12:12 pm, Michael S <already5cho...(a)yahoo.com> wrote: On Jul 6, 11:00 am, Frank van Eijkelenburg <fei.technolut...(a)gmail.com> wrote: I hope to fix the problem before my vacation (only one day left :) Something, I most certainly DO NOT RECOMMEND for final solution, but it could help to g... 12 Aug 2010 14:45
Spartan3a: improving DCM performance and "To achieve optimal frequency synthesis performance..." warning On Aug 10, 8:43 pm, Philip Pemberton <usene...(a)philpem.me.uk> wrote: Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_gener... 11 Aug 2010 21:20
Spartan3a: improving DCM performance and "To achieve optimalfrequency synthesis performance..." warning Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet. This is on a Sparta... 10 Aug 2010 22:25
Best clock output pin in Spartan-3 Same question. Does anybody know it? --- news://freenews.netfront.net/ - complaints: news(a)netfront.net --- ... 10 Aug 2010 20:13
Instantiating non-global clock buffers (Xilinx ISE) I have a design with too many global clocks which ISE automatically adds. Some of these clocks are slow and feed into relatively small areas of logic. Is there a way I can specify these clocks to be non-global? ... 11 Aug 2010 14:43 |