FPGA
in [Hardware]
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Last Call for Papers Reminder (extended): World Congress on Engineering and Computer Science WCECS 2010 Last Call for Papers Reminder (extended): World Congress on Engineering and Computer Science WCECS 2010 CFP: World Congress on Engineering and Computer Science WCECS 2010 Draft Paper Submission Deadline (extended): 26 July, 2010 Camera-Ready Papers Due & Registration Deadline (extended): 16 August, 2010 WCECS 2... 16 Jul 2010 04:27
1-wire question HI all, I would like to write a decoder for 1-wire but I am stuck about the search algorithm. My question is: is it possible for a third party, without knowing the 1-Wire master and "slave" status, to correctly decode the whole execution of the command? I mean, the sequence of bits exhanged on the bus coul... 16 Jul 2010 02:19
DDRé SDRAM configuration hi all, I want to implement a DDR2 SDRAM controller, as Xilinx provides MIG software tool to create IP core for the memory interface, however I have some questions about the port configuration. I want to store up to 9 frames(3000H x 2748V) of image data into 1GB DDR2 SDRAM(MT47H64M16), the frame size is resoluti... 22 Jul 2010 04:51
Another Xilinx webpack download rant Hello I've been trying to download these 2.9GB for 3 days with numerous retries (thanks to the download manager, the 'resume' resulted in a restart from 0) and when I finally managed to get the full file it was corrupted. Now I want to order a DVD and when I click on the appropriate link on the web site I get red... 19 Jul 2010 11:18
help regarding daisy chained fpgas Hello! I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain on a custom board. The problem is when i program my FPGAs through JTAG interface, FPGA 1 always gets programmed and verified and always shows output whereas FPGA 2 always gets programmed and verified and sometimes it shows the output and ... 16 Jul 2010 09:52
Verilog in Quartus and assignments in blocks I was under the impression that in Verilog nonblocking assignments are evaluated in an arbitrary order. However, in Quartus, I have noticed that if you use something like this: always @(posedge clock) begin a <= 1; if (condition) a <= 0; end Then, if "condition" is true "a" will always be assigne... 15 Jul 2010 15:23
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WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing... Hi guys, I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint Drigmorn2 development board. Basically, the SDRAM is acting like the mythical Write Only Memory -- I can write stuff to it, but as soon as the address goes over 0x800, the readback is stuffed. Does anyone have either a known-... 17 Jul 2010 06:35
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