FPGA
in [Hardware]
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Expand TEMAC fifo? Hello, I'm working on an embedded project (EDK 11.2) and am using the TEMAC IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo). From what I can tell, the size of the Tx fifo is only 2Kb; this causes a bit of an issue for me: I am using my embedded project to stream 20 byte words over Ethernet. Right now, ... 18 Jun 2010 21:15
Decoupling for Altera Cyclone II 2C8 Hi guys, I'm designing a PCB for a project of mine (a floppy disc data analyser -- see <http://www.discferret.com/>). This will be my first project with an FPGA, or at least the first one that's made it as far as actual PCBs being made. I'm using an Altera Cyclone II EP2C8 in TQ144 (144-pin TQFP) package. T... 16 Jun 2010 12:08
DLC9G problem Hi all dear I have a DLC9G programmer for programming all FPGAs It was working good but from some days before I don't know why but after connecting programmer to board the LED is getting green but when I select Initialize chain in impact software I have an error that it says you don't have adequate voltage and some th... 15 Jun 2010 08:40
Trouble with Altium Openbus document based UART example using TSK3000A Dear Friends, i am using Altium Designer for fpga and embedded project on digilent spartan3E-500 board. I have created an FPGA project in Altium using open bus document containing three device: 1. TSK3000A 2. WB_PRTIO_1 (for leds) 3. WB_UART_V2_1 Added a top level schematic sheet. Added constraint file ... 17 Jun 2010 10:01
Simulation error Hi guys, When i try to simulate a simple EXOR i get the following error: # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Licensing checkout error with feature x... 15 Jun 2010 08:40
VIRTEX5 (XUPV5-LX110T) Ethernet Hi, Im working on communication for the Virtex 5 using Ethernet. As a good start, do you have any ideas/examples program which use Virtex5? I have tried browsing on the internet, but there are not much about Ethernet Virtex5 example codes. I would be very happy if somebody can guide to show a simple program to commun... 15 Jun 2010 08:40
How to detect a sync and start of a frame in an optimal way Hi All I am designing a module and I am having some issues .. Let me explain what I am doing. I am getting data as 64 bytes in each clock cycle . In these 64 bytes I look for sync bits which is "01" and then a fixed pattern of "1111" for the start of the frame . The next byte tells us the length of the payl... 17 Jun 2010 07:50
Does Xilinx Spartan 6 support NAND flash? According to the datasheet, The Spartan 6 family has Broad third-party SPI (up to x4) and NOR flash support Feature rich Xilinx Platform Flash with JTAG I don't quite understans if it supports NAND flash? I want to build and FPGA + ARM platform, each component has their own flash. How do you think, should I u... 15 Jun 2010 10:53
Trouble with Altium Openbus document based UART example using TSK3000A Dear Friends, i am using Altium Designer for fpga and embedded project on digilent spartan3E-500 board. I have created an FPGA project in Altium using open bus document containing three device: 1. TSK3000A 2. WB_PRTIO_1 (for leds) 3. WB_UART_V2_1 Added a top level schematic sheet. Added constraint file to the... 14 Jun 2010 13:58
how fast is ... fast. Hi, In a design I'm working on I have a machine that produces 128 bit of data. This data is destined to a 16 bit DAC running 8x faster. Knowing that I can produce the 128bit up to a 120MHz rate I wanted to generate the 8x 16bit stream as fast as I can (and I'm using a 500MHz DAC) The 128 to 16bit It's all ... 22 Jun 2010 07:10 |