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Burn to an internal prom Spartan-3an
I use an internal memory Spartan 3an When I try to burn only the FPGA I can! Even when I try to burn the FPGA and the prom I get in the middle of the recording process failed! And the reason he failed is: "'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configu... 7 Jun 2010 10:44
Calling different modules of a project from another main file
Hello Friends Our group has finished a project which has different modules in it, executing different tasks. We need to call this different modules of the project from a different main file. For callling each module, I have set a single bit input port for each module in the project... 7 Jun 2010 14:17
Verifying/comparing the FFT output between Xilinx Coregen block and Matlab´┐Żs fft function
On Thu, 3 Jun 2010 13:19:18 -0700 (PDT), Vivek Menon <vivek.menon79(a)gmail.com> wrote: Alan: Thanks for these tips. 2. Look for being off by an output stride permutation or transpose. I am not sure how to check this. Can you elaborate ? You started quite well, in your previous post. You observed:... 4 Jun 2010 10:18
ISE Design Suite 11 will not evaluate 2's comp
If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! According to this information [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] ISE 11 should be running verilog 2001, however when I try to run the arithmetic shift ">>>" it does not populate 1's for negative numbers as it s... 3 Jun 2010 16:45
ISE Design Suite 11 will not evaluate 2's comp
If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! According to this information [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] ISE 11 should be running verilog 2001, however when I try to run the arithmetic shift ">>>" it does not populate 1's for negative numbers as it s... 3 Jun 2010 14:30
ISE Design Suite 11 will not evaluate 2's comp
If anyone out there uses Xilinx ISE Design Suite 11, I need your help!! According to this information [link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link] ISE 11 should be running verilog 2001, however when I try to run the arithmetic shift ">>>" it does not populate 1's for negative numbers as it s... 3 Jun 2010 14:30
Call for Papers: World Congress on Engineering and Computer Science WCECS 2010
CFP: World Congress on Engineering and Computer Science WCECS 2010 Draft Paper Submission Deadline: 2 July, 2010 Camera-Ready Papers Due & Registration Deadline: 30 July, 2010 WCECS 2010: San Francisco, USA, 20-22 October, 2010 http://www.iaeng.org/WCECS2010 The WCECS 2010 is organized by the International Assoc... 3 Jun 2010 06:43
Spartan6 power consumption
Hi, Have you got some examples of Spartan6 power consumption betwwen differents configurations? Thank you ... 3 Jun 2010 05:38
Spartan-6 hold time problems (multipost to Xilinx forums)
I've got a Spartan-6 design with two different clocks. They're generated from the same 20 MHz reference on two PLLs, and are called WB_SYS.CLK_I (50 MHz) and clk128. They're treated as entirely asynchronous by the design logic, and data passing between them is safe by design, and so in order to get rid of the... 3 Jun 2010 04:33
How good are Actel tools
> Can anyone confirm or dispute it the relative quality of Actel tools? Am I mistaken about them? Rick I've not used a wide range of FPGA tool suites, just the other major two, but I have found that Actel's, have been the worst yet. I don't do very large of complex designs, just stuff for single FPGA... 3 Jun 2010 12:15
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