First  |  Prev |  Next  |  Last
Pages: 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Question about PCB CAD for FPGA-based project
Hello, I am a beginner interested to learn what PCB design software is suitable for designs using FPGA chips? I also wonder whether free software packages (such as FreePCB, ExpressPCB) are good enough for PCB designs using FPGA chips? Thank you. P.S. As I use Spartan3E 1600E Microblaze Development Boar... 28 Apr 2010 11:41
Virtex 4 ICAP partial reconfiguration
I have built a design with PR flow 9.2 using bus macros. The dynamic reconfiguration works using Impact and downloading the partial bistreams. I have connected the Virtex 4 ICAP port to the LEON3 processor through the AMBA APB bus. I would like to perform partial reconfiguration through ICAP. I have a C software... 27 Apr 2010 12:08
Reading UDP with FPGA
>Hi all, as the title says I have to read some information stored in UDP packet with an FPGA. Now I'm evaluating 3 options: 1) Use an external processor and send data to FPGA through dedicated lines 2) Use a microcontroller embedded into the FPGA (i.e. microblaze, since I'm working on a Xilinx) 3) W... 27 Apr 2010 12:08
Ethernet development kit
>Hi folks, I would like to ask you for recomandation of the ethernet development kit with FPGA (much preferably Xilinx's one). Our requirements are the low power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. I am not sure it there is currently such kit being distributed, because I was... 27 Apr 2010 10:59
Writing Hex values to file in VHDL?
>I'm trying to dump eight hex values per line into a file, and can't work out how to do it. for index in 0 to 127 loop for sample_sel in 0 to 7 loop sample_val := integer(scale * sin(phase(sample_sel))); write ( sample_line, sample_val, RIGHT, 10); phase(sample_sel) := phase(sample_... 27 Apr 2010 10:59
Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
Hi, I am implementing BMD design as explained in xapp1052(v2.5). Have implemented the design on AvnetV5LXT/SXT PCIe Development Board using the PCIe. Have generated the EndpointBlock plus for PCIe 1.9 using ISE 10.1. I have 2 board of Virtex-5 LXT/SXT PCIe Board which i am using to run two machine of INTEL i.e S... 28 Apr 2010 11:41
ISE tools not detecting IOSTANDARD conflicts within bank
Hello, I'm running ISE 9.2.03i on a design for Spartan 3E (3s250e-4tq144). For whoever wishes to skip the long description below, the idea is simple: The tools should not agree to place pins with conflicting IO standards, such as LVTTL and LVCMOS25, on the same bank. And suddenly I caught the tools not noticin... 1 May 2010 02:14
Booting Linux from my own bootloader
Hello, I'm writing a boot loader to start Linux on the PowerPC440 (Virtex5FXT). At first the program copies the kernel into the RAM at address 0x00400000 and afterwards it boots Linux with the following lines: #define LINUX_START_ADDRESS 0x004002b4 int main() { void (*linux)(); linux = (void*) LINUX_STA... 30 Apr 2010 05:05
Inferring mutipliers
Challenge : 18*18 data with one data vector unsigned and the other signed. FPGA DSP block actually has separate signals to set the sign of each operand. If the operands are the full data width of the DPS block inputs it is not possible to "sign... 28 Apr 2010 03:56
I am using data2mem to generate some .mem simulation files. My address for memory starts at 0x86000000 and if I dump the elf file I can see that. However when I run data2mem the .mem file starts at address 0x00000000. The command I am using is data2mem -bd memory_init.bmm -bd test.elf -bx -u -i and my bmm loo... 26 Apr 2010 10:14
First  |  Prev |  Next  |  Last
Pages: 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38