FPGA
in [Hardware]
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Which is the most beautiful and memorable hardware structure in a CPU? In comp.arch.fpga Jason Zheng <Xin.Zheng(a)jpl.nasa.gov> wrote: (snip) My favorite is the Translation Look-aside Buffers (TLB), of course invented by the IBM engineers. You have to appreciate the way it sounds (and its irrelevance to its true purpose). If you read the IBM description of virtual storage, y... 2 Apr 2010 00:38
Which is the most beautiful and memorable hardware structure in a CPU? In article <hosgq9$h5m$1(a)smaug.linux.pwf.cam.ac.uk>, nmm1(a)cam.ac.uk says... In article <27ebdb37-e3ba-4559-be7d-d7f3b6613d77(a)30g2000yqi.googlegroups.com>, MitchAlsup <MitchAlsup(a)aol.com> wrote: The most memorable hardware structure is the vector indirect addressing mode. Yes. There were and are mo... 30 Mar 2010 13:51
Using Verilog Macros with Arguments Hi all, I want to used parameterized Verilog macros in my code. It looks somewhat as shown below: //////////////////////////////////////////////////////////// `define ACTIVE_EDGE posedge parameter ISO_SENSE=1; always @(`ACTIVE_EDGE isolation_ctrl) if(isolation_ctrl==ISO_SENSE) ... 3 Apr 2010 07:09
MSI for BMD design hi i am working on BMD design and using xapp1052 to implement it. I need to use multiple vectors for doing MSI to use it with my application. Can anyone guide me how can i do it or refer to some material which can help me doing it. Regards Usama ... 30 Mar 2010 08:17
MSI for BMD design hi i am working on BMD design and using xapp1052 to implement it. I need to use multiple vectors for doing MSI to use it with my application. Can anyone guide me how can i do it or refer to some material which can help me doing it. Regards Usama ... 30 Mar 2010 08:17
Spartan 6 PLL - Why such a strict input jitter requirement? Hi there, Looking for insight here - Spartan 6 adds a PLL to the mix and we wondered to what extent it can be used to filter jitter, for example for a Synchronous Ethernet product requirement we have. However, the SP6 PLL seems to have a very stringent max input jitter requirement. It does not allow an input clock... 2 Apr 2010 13:42
Spartan 3E: MAX_STEPS as a function of CLKIN frequency Hello, I'm trying to figure out how much delay variance I can achieve using the variable phase shifter on a Spartan 3E device. I may change the input frequency if that helps me, and use the CLKFX output as target clock, so basically I need to figure out how to choose CLKIN wisely to get an adequate phase shift. ... 1 Apr 2010 17:58
Free VHDL or Verilog Simulator Hi, Altera's Quartus II does not include a free simulator. Is there a free VHDL or Verilog simulator that is reasonalbly good? Google shows a few but I would prefer a recommendation. Thanks, Gary ... 27 Apr 2010 09:51
infering BRAM for a FIFO in XST(spartan 3) Hello, I want to tell XST that uses block RAM for my FIFO, but I couldn't till now. can you please take a look at my code and tell me what should I do ? http://openpaste.org/en/20191/ thanks ... 30 Mar 2010 00:42
Xilinx Webpack v11.4 availability Hello, Could someone please clarify if Webpack v11.4 is available for download. I am trying to download Webpack from the following link http://www.xilinx.com/tools/webpack.htm However it seems like v11.1 is the latest version available on Xilinx's wesite. Thanks in advance. Regards, Vikram. ... 30 Mar 2010 17:13 |