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Using bidirectional pins in Verilog
I'm trying to use bidirectional pins in Quartus with Verilog. What's the correct way to do it? Altera has some example code: But I don't really understand it. For example, it says it can drive the value b out but I can't see bidir being assigned ... 3 Mar 2010 16:23
Embedded Industry Expert Opinions Needed
VDC is conducting its annual survey of mobile and embedded engineers so if you are involved in the engineering of mobile or embedded systems/software, this is your chance to influence key solution suppliers. The research covers embedded software, hardware, tools, and development practices. Your thoughts will imp... 3 Mar 2010 12:58
Xilinx IOBUF - operation Q (virtex4 chip)
Hi All, I got this newbie Q I hope to get answer for. I'm looking at some example code sent to me by outside contractor, the code makes use of inout ports of the FPGA: -- begin quote IOBUF1 : IOBUF16 port map(DIN => PCI_data(31 downto 16) , DIO => SABD(15 downto 0), DOUT=> SABD_i(15 downto 0), T => PCI_en... 3 Mar 2010 15:14
Laptop for FPGA design?
I'm going to be travelling soon, and will continue to do FPGA design from the road. I'll need to get a new laptop for this. Any thoughts? I think something based on the Core i7-620M might be fast enough and low power, but they seem rare. Looks like I'll probably end up with something with a Core i7-720QM or a ... 7 Mar 2010 12:55
Modelsim PE vs. Aldec Active-HDL (PE)
I've finally decided to buy a better simulator (I've been making do with Modelsim XE so far). Any thoughts as to the relative merits of Modelsim PE and Active-HDL (PE) for FPGA simulation? Thanks Pete ... 5 Apr 2010 14:57
I've just noticed and read the thread you started just before Christmas about your Fifo problem. You said... problem fixed! solution and explanation in the next Brain issue (I will post short post also after the issue release) Any sign of the new Brain? BTW, was the read indicated by a single clo... 4 Mar 2010 14:37
Tabula. (FPGA start up)
This lot seems to be revealing a bit more about their stuff. ... 18 Mar 2010 03:43
Need support for differential 1.2V IOStandard on Virtex-6
Hi all, I'm designing an LPDDR2 SDRAM memory interface controller for a Virtex-6 FPGA based on the DDR3 interface controller provided by MIG 3.3. The memory interface signals need a 1.2V IOStandard. For the single- ended signals, either LVCMOS12 or HSTL_I_12 IOStandard can be used. The problem is on the diffe... 1 Mar 2010 22:04
LVDS i/o in a SystemVerilog Interface block
I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that LVDS i/os should only be instantiated using a megafunction. But the interface blocks do not allow hierarchy so I cannot instantiate a megafunction inside the interface block. A... 2 Mar 2010 12:20
Spice simulation of IBIS details - model examples
As a simple exercise, I looked at the info in a IBIS file, which is quite simple : V-I tables, and pF and nS values for ramps. So if you have a simple problem : What clock edge should I finally get ?, you can create a napkin Spice model, that can be used to track bench tests. The V-I tables can give the ou... 2 Mar 2010 14:38
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