Spice simulation of IBIS details - model examples
in [FPGA]
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From: -jg on 1 Mar 2010 03:17 As a simple exercise, I looked at the info in a IBIS file, which is quite simple : V-I tables, and pF and nS values for ramps. So if you have a simple problem : What clock edge should I finally get ?, you can create a napkin Spice model, that can be used to track bench tests. The V-I tables can give the output impedance. For overshoot, use the N- CH values, and for min-slew checks, use the (usually slightly higher) P-CH values. Slew values are used to set the PWL source, and R/C values here I have split in two, and modeled, with a third C/2 for trace/load capacitance.. example for a 30 ohm, 10pF and 1ns or 2ns ramp values 22nH parasitic L. This has two instances to show slew-range effects on one plot. It is also small enough to easily fit inside most demo-mode Spice's [ Tested on B2spice / LTSpice / SpiceOpus. ] -jg ~~~~~~~~ Edited to be more human-understood ~~~~~~~ ***** main circuit V1 1 0 PWL ( 0 0 + 50n 0 + 52n 3.3 + 100n 3.3 + 102n 0) R1 1 2 15 C1 2 0 5p R2 2 3 15 C2 3 0 5p L1 3 4 22n C3 4 0 5p IV2ns 4 0 0 V2 5 0 PWL ( 0 0 + 50n 0 + 51n 3.3 + 100n 3.3 + 101n 0) R3 5 6 15 C4 6 0 5p R4 6 7 15 C5 7 0 5p L2 7 8 22n C6 8 0 5p IV1ns 8 0 0 ..TRAN 1E-9 1.2E-7 3E-8 1E-9 ..OPTIONS temp = 27 ..end ~~~~~~~~~~~~~ LTSpice, B2Spice ~~~~~~~~~~ * IBIS_Check.cir for LTSpice * ***** main circuit V1 1 0 PWL ( 0 0 + 50n 0 + 52n 3.3 + 100n 3.3 + 102n 0) R1 1 2 15 C1 2 0 5p R2 2 3 15 C2 3 0 5p L1 3 4 22n C3 4 0 5p IV2ns 4 0 0 V2 5 0 PWL ( 0 0 + 50n 0 + 51n 3.3 + 100n 3.3 + 101n 0) R3 5 6 15 C4 6 0 5p R4 6 7 15 C5 7 0 5p L2 7 8 22n C6 8 0 5p IV1ns 8 0 0 ..TRAN 1E-9 1.2E-7 3E-8 1E-9 * PickVisibleTraces V(8) V(4) then File.SavePlotSettings ..end http://www.spiceopus.si/download/downloadw.html ~~~~~~~~~~~~~ SpiceOpus ~~~~~~~~~~~~~~~~ * IBIS_Check.cir for SpiceOpus * ***** main circuit V1 1 0 PWL ( 0 0 + 50n 0 + 52n 3.3 + 100n 3.3 + 102n 0) R1 1 2 15 C1 2 0 5p R2 2 3 15 C2 3 0 5p L1 3 4 22n C3 4 0 5p IV2ns 4 0 0 V2 5 0 PWL ( 0 0 + 50n 0 + 51n 3.3 + 100n 3.3 + 101n 0) R3 5 6 15 C4 6 0 5p R4 6 7 15 C5 7 0 5p L2 7 8 22n C6 8 0 5p IV1ns 8 0 0 * SpiceOpus script control section follows .control, this section is less spice portable ..control destroy all tran 1E-9 1.2E-7 3E-8 1E-9 * was .TRAN 1E-9 1.2E-7 3E-8 1E-9 run rusage time setplot setplot tran plot v(8) v(4) xlabel t[s] ylabel '1nS Rise(r), 2nS Rise(g)' ..endc ..end
From: Jared Casper on 1 Mar 2010 04:30 On 03/01/2010 12:17 AM, -jg wrote: > The V-I tables can give the output impedance. For overshoot, use the N- > CH values, and for min-slew checks, use the (usually slightly higher) > P-CH values. > I'm not sure if it is that straight forward. From "The Development of Analog SPICE Behavioral Model Based on IBIS Model" Ying Wang and Han Ngee Tan, Proceedings of the Ninth Great Lakes Symposium on VLSI, (March 1999) http://www.cecs.uci.edu/~papers/compendium94-03/papers/1999/glsvlsi99/pdffiles/glsvlsi99_101.pdf > It must be cautioned that the IV tables of an IBIS > model are purely based on DC condition and should not > be used for transient simulation. .... > Thus, the approach of deriving switching signal only > based on static information, i.e., DC IV tables is not > valid. The dynamic information provided by IBIS model > must be adopted in the generation of analog SPICE > behavioral model. The model building principle is to map > all IBIS information of both static and dynamic into the > SPICE model. I would recommend a read through of that paper if you want to make a SPICE model based on IBIS data (it is only four pages long). This paper is built on the methodology presented in this paper, which gives a bit more info: "Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS" - by Peivand Tehrani, Yuzhe Chen and Jiayuan Fang, 46th IEEE Electronic Components & Technology Conference (May 28-31, 1996) http://www.sigrity.com/papers/ectc96/ectc96ibis.pdf Jared Casper
From: -jg on 1 Mar 2010 05:05 On Mar 1, 10:30 pm, Jared Casper <jaredcas...(a)gmail.com> wrote: > On 03/01/2010 12:17 AM, -jg wrote: > > > The V-I tables can give the output impedance. For overshoot, use the N- > > CH values, and for min-slew checks, use the (usually slightly higher) > > P-CH values. > > I'm not sure if it is that straight forward. From > > "The Development of Analog SPICE Behavioral Model Based on IBIS Model" > Ying Wang and Han Ngee Tan, Proceedings of the Ninth Great Lakes > Symposium on VLSI, (March 1999)http://www.cecs.uci.edu/~papers/compendium94-03/papers/1999/glsvlsi99... > > > It must be cautioned that the IV tables of an IBIS > > model are purely based on DC condition and should not > > be used for transient simulation. > ... > > Thus, the approach of deriving switching signal only > > based on static information, i.e., DC IV tables is not > > valid. The dynamic information provided by IBIS model > > must be adopted in the generation of analog SPICE > > behavioral model. The model building principle is to map > > all IBIS information of both static and dynamic into the > > SPICE model. > > I would recommend a read through of that paper if you want to make a > SPICE model based on IBIS data (it is only four pages long). > > This paper is built on the methodology presented in this paper, which > gives a bit more info: > > "Extraction of Transient Behavioral Model of Digital I/O Buffers from > IBIS" - by Peivand Tehrani, Yuzhe Chen and Jiayuan Fang, 46th IEEE > Electronic Components & Technology Conference (May 28-31, 1996)http://www..sigrity.com/papers/ectc96/ectc96ibis.pdf > > Jared Casper Yup, which is why the spice model I have, is not using just R. It also includes these AC parameters a) Slew rate value b) Capacitance c) Inductance -jg
From: rickman on 1 Mar 2010 18:56 On Mar 1, 4:30 am, Jared Casper <jaredcas...(a)gmail.com> wrote: > On 03/01/2010 12:17 AM, -jg wrote: > > > The V-I tables can give the output impedance. For overshoot, use the N- > > CH values, and for min-slew checks, use the (usually slightly higher) > > P-CH values. > > I'm not sure if it is that straight forward. From > > "The Development of Analog SPICE Behavioral Model Based on IBIS Model" > Ying Wang and Han Ngee Tan, Proceedings of the Ninth Great Lakes > Symposium on VLSI, (March 1999)http://www.cecs.uci.edu/~papers/compendium94-03/papers/1999/glsvlsi99... > > > It must be cautioned that the IV tables of an IBIS > > model are purely based on DC condition and should not > > be used for transient simulation. > ... > > Thus, the approach of deriving switching signal only > > based on static information, i.e., DC IV tables is not > > valid. The dynamic information provided by IBIS model > > must be adopted in the generation of analog SPICE > > behavioral model. The model building principle is to map > > all IBIS information of both static and dynamic into the > > SPICE model. > > I would recommend a read through of that paper if you want to make a > SPICE model based on IBIS data (it is only four pages long). > > This paper is built on the methodology presented in this paper, which > gives a bit more info: > > "Extraction of Transient Behavioral Model of Digital I/O Buffers from > IBIS" - by Peivand Tehrani, Yuzhe Chen and Jiayuan Fang, 46th IEEE > Electronic Components & Technology Conference (May 28-31, 1996)http://www..sigrity.com/papers/ectc96/ectc96ibis.pdf > > Jared Casper I can attest to the fact that there are things going on that are very different from the static conditions. I ran an IBIS simulation on the file provided by the vendor... actually, I don't thin it was a simulation as much as just a display of the waveform shown in the IBIS file. It clearly shows a quick rise time (~1 ns) to a level lower than Vdd because of the 100 ohm load to ground. But after about 2-3 ns the voltage drops off and remains constant for the duration of the 20 ns data sample. I am pretty sure you can't generate this waveform with a simple RLC model. It also makes me suspicious of the entire IBIS file thing. It just seems like this is a very poor way to model an I/O, but then I haven't looked at it in detail. I do know that the one time I used a simulator, it did not give results so much like what we measured. It predicted severe overshoot on the bus lines and we observed very little. Rick
From: -jg on 1 Mar 2010 19:11
On Mar 2, 12:56 pm, rickman <gnu...(a)gmail.com> wrote: > It clearly shows a quick rise time (~1 ns) to a level lower > than Vdd because of the 100 ohm load to ground. But after about 2-3 > ns the voltage drops off and remains constant for the duration of the > 20 ns data sample. I am pretty sure you can't generate this waveform > with a simple RLC model. It also makes me suspicious of the entire > IBIS file thing. Yes, that sounds simply broken. Like the sim-engine, and the model got out of step. Did your scope 'reality check' look anything like that? > It just seems like this is a very poor way to model > an I/O, but then I haven't looked at it in detail. IBIS is simplified output from the 'real spice'. So they just have single numbers for ramp rates, and a table plot for I-V. Given the limits of the information in the IBIS, you should still be able to get useful spice data points. Certainly more than enough, to correlate with bench measurements, and for clock ringing (which is what you were looking for). Tho I'm not sure I'd try and get Eye patterns from it ;) It's best to use Hyperlynx for that level of analysis. Those spice examples look quite plausible to me. Both show ringing, but with (expected) quite different amplitudes and phases. |