FPGA

Question in verilog testbench
Hi, all I have a question in the testbench written by verilog. Why we always define the inputs of MUT as reg and outputs of MUT as wire, just the opposite with the in/output definition in verilog modules. So more clearly, what are the basic issues that I should know when I have to decide the type of a variable(r... 7 Mar 2010 09:35

Display Control Application Using Spartan FPGA
Hi folks, I have been introduced to a project where I have to implement a TFT display controlller on a low-cost FPGA like Spartan-3 or Spartan-6. The controller has to support at least XGA - 1024x768, SXGA - 1280x1024, UXGA - 1600x1200 and WUXGA 1920x1200. I have to chose an appropriate platform now. As I am a... 6 Mar 2010 10:43

FSM in BlockRAM
Hello to all ! I've problem with finite state machine. Because I have not much place in my FPGA and I need to create few more FSM i found that FSM logic can be packed in to BRAM. I created simple FSM in VHDL and it shows in raport that it uses Bram but there is a warning : WARNING:Xst - Cannot use block RAM reso... 6 Mar 2010 19:34

Programmable Logic Controllers (James A. Rehg, Glenn J. Sartori) solutions manual
I have solutions manuals for these scientific textbooks .. They are all in PDF format .. If you are interested in any one, simply send me an email to macmorino(at)gmail(dot)com .. Please this service is NOT free. Here are solutions manuals to some titles.. Instructor's solutions manual for A Course in Modern M... 4 Mar 2010 22:31

Is an inout reg allowed
I've tried to use an inout reg with quartus and it doesn't give a warning. However, I read on the internet that an inout port can only be a wire. Which one is true? ... 5 Mar 2010 13:54

CFP with Extended Deadline of Mar. 21, 2010: The 2010 International Conference on Embedded Systems and Applications (ESA'10), USA, July 2010
It would be greatly appreciated if this announcement could be shared with individuals whose research interests include embedded systems. Thank you. ------- CALL FOR PAPERS Paper Submission Deadline (EXTENDED): March 21, 2010 ESA'10 The 2010 Inte... 4 Mar 2010 18:02

Actel is now the only FPGA vendor with hard-core processor in the latest family
as Xilinx has dropped hard processor IP in the latest families it makes ACTEL the only FPGA vendor whos latest product family does have hard processor IP. Smart fusion includes Cortex-M3, and yes its available now, I did have the kits in my hand at embedded Antti ... 5 Mar 2010 17:19

Announce: 1 Pin Interface - FPGA and HW debug tool
On Mar 4, 5:31 am, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: www.1pin-interface.com I've been emailed to say that some people are having problems with this. This is based on a Tiddlywiki, a quick google shows that the Skype plug-in breaks some wiki-sites. It's in the Sk... 5 Mar 2010 05:01

Ethernet development kit
Hi folks, I would like to ask you for recomandation of the ethernet development kit with FPGA (much preferably Xilinx's one). Our requirements are the low power, as big FPGA as possible and at least 3 ethernet ports at 1Gbps. I am not sure it there is currently such kit being distributed, because I was not ab... 6 Mar 2010 10:43

Announce: 1 Pin Interface - FPGA and HW debug tool
A few years ago I designed a small prototype board to allow access to an FPGA internal registers via a single bi-directional pin. This replaces an RS232 type interface but is USB driven so removes the need for external power supplies for level shifters etc. This has been invaluable, I've used it with almost eve... 4 Mar 2010 07:49