FPGA
in [Hardware]
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USB Blaster Does anybody know how to program access to the Altera USB Blaster? I am trying to port Altera's SRunner software, which currently only supports a ByteBlaster II on a Windows environment to support the USB Blaster (since this is the only download cable I have) on either Windows or Linux. Any help would be appreci... 22 Aug 2005 04:29
Evolutionary VHDL code example Hello everyone Does anyone where I can find a simple VHDl code example based on evolutionary algorithms.I am doing a project on evolvable hardware. This will help me get a start on the implementation of Evolvable Hardware. Ankit Parikh Manukau Institute Of Technology ... 20 Aug 2005 18:19
NIOS II + USB 2.0 host Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP co... 17 Jul 2005 22:07
Xilinx: XST synchronous FIFO using BRAMs Dear all, Lately I have been trying to design and implement a synchronous FIFO using a cyclic buffer, that can be synthesized by XST to use Block RAMs. I now have a version that works (it does so in simulation using GHDL). I have attached it below. However, since it doesn't follow the prescribed pattern for... 6 Jul 2005 07:14
errors during MAP Hello, Could you, please, give any insight on what can cause the following errors (i got many)? I also have the same errors on the internal signals, not only xilinx nets. Thanks Vladislav ------------------------------------------------------------------------------------ ERROR:MapLib:661 - LUT4 symbol ... 14 Jun 2005 12:56
Problem for xilinx!!! hi....Please help me for a programmer xilinx XC9536XL (parallel LPT) When i starter to program, it stopped on: "Error:IMPACT 583 :the idcode read from the device does not match the idcode in the bsdl" :( Help me thanks a lot..... ... 5 Jul 2005 02:30
ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins... I am getting the following warning on a Virtex-II design: WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. My question is how can I find the problematic pin? A similar question was asked here in the past, but the discussion slipped into ... 13 Jun 2005 21:38
I2C clock stretching(XILINX reference design) Hi all, I am implementing a I2C slave. I am refering XAPP333 for my deisgn. But one of the "limitation" of that reference design from XILINX is that it does not support "clock stretching". Suppose we do not need clock stretching "SCL" will be taken as INPUT to my I2C slave block.But if i want Clock stretching ... 10 Jun 2005 18:05
FPGA Boards Link to a good selection of FPGA based boards: http://www.hitechglobal.com/Boards/allboards.htm as well as IP Cores for FPGA and ASIC http://www.hitechglobal.com/ipcores/default.htm ... 31 May 2005 16:01
Virtex4 running at 360Mhz DDR I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like hear what others think and perhaps point out where I need to be careful in the design. I'd be receiving an LVDS clock pair @ 360Mhz, running part of the internal logic at 360. This internal log... 31 May 2005 17:38 |