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Xilinx, MIG, UCF: timing constraints for DDR2 DRAM
Hi FPGA Group! I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM interface, generated with the Xilinx Memory Interface Generator. The complete system consists of a PCI interface, an I/O DMA buffer, a burst module bursting from DMA buffer to the DDR2 DRAM interface. What is the best way to def... 10 Nov 2007 08:21
builing a SPI interface in vhdl
HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let an fpga read and write a flash memory. The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 (serial I/O). Do you know if is there any built vhdl core to start with? Thanks in advance Giulio ... 10 Nov 2007 08:21
XILINX CDs please send e-mail to : ola 'AT' mail 'DOT' gr , ola3 'AT' mailbox 'DOT' gr , www 'DOT' 20000plusdvdsandcds 'DOT' tk , ( please substitute 'AT' with '@' , and 'DOT' with '.' ) , ola(a), ola3(a), --------------------------------------- XiLiNX FOUNDATION V2.1... 23 Oct 2007 10:20
LEDs, buttons and LCD
Hello folk! Hello, I have just bought Spartan 3E-1600E Microblaze Development kit and I am complete beginner. Really want to learn FPGA programming but have no idea what this board is for. For example, the LEDs (all are green) - what they really represent?... and LCD? Can I print something on it? ... 25 Oct 2007 08:37
Hi, i get this message when i run post & route: Starting Placer FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of library <C:/Xilinx91i/xilinx/bin/nt/libPlXil_Clocks.dll> failed due to an unknown reason. Process will terminate. Process "Place & Route" failed Could somebody help me? ... 28 Sep 2007 23:24
Hi. Does somebody have a real success with burning OpenSPARC to FPGA? ... 5 Aug 2007 15:40
SDR SDRAM controller for Xilinx Spartan-3E
Hello, I would like to utilize a controller for a SINGLE data rate SDRAM (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended up pretty happy with (after forgetting the via dolorosa to set it up...). Its main benefit is a simple and conveni... 12 Aug 2007 04:01
Spartan 3E starter kit DDR SDRAM
I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread. Is there such a demo out, mentioned in the thread? I read in several groups that it is a problem to get this DDR Ram running ? ... 4 Aug 2007 19:35
Microblaze Interrupt Handler
Hi All, I'm beginner for Microblaze. I use Spartan3E eval kit. I want to create custom ip and use interrupt. 1 - I create custom ip, connect it to OPB then I connect ports. I'm trying my ip on the board and it is ok. My ip is working without a problem. 2 - I create a line in mhs file (there is no another interr... 30 Jul 2007 07:20
Convert Schematic Files (.sch) to Verilog Files (.v) for simulationin ModelSim
Craig, Depending on what tools you used to capture the schematic, and what models your flow supports, asking for a "verilog netlist" is a feature of some tools. The resulting verilog netlist will be at the transistor and wire level, or gate level (which in the hierarchy is made up of gates and wires), and wil... 13 Jul 2007 10:51
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