Xilinx ISim and FSM states names
Hello, I'm simulating a FSM written in Verilog using Xilinx ISim. Is there any possibility to see in waveform the FSM state names instead of just numbers, which I have to manually decode to state names? Regards, Misiu ... 18 Oct 2009 08:22
Any interest in a group Xilinx FPGA board build/buy ??
Is there any interest in a group buy & design of a Xilinx fpga board ? I would like a fairly large Spartan FPGA + lots of IO expansion + low cost $200 - $250 usd. The exisiting FPGA boards on the market seems either too expensive or small FPGA or too little expansion potential. The idea is to get a high capac... 20 Oct 2009 22:18
Controller to access internal FPGA registers from JTAG
Hi, I just had to debug separately a system which usually works connected to the asynchronous parallel bus (address and data busses, read and write strobe). The system was connected to my development box via the JTAG interface (used to configure FPGAs), so I wanted to use the same interface to access the intern... 16 Oct 2009 18:31
Does anyone have current contact details for Jerry D. Harthcock?
Hello, Does anyone know how to contact Jerry Harthcock? Yours faithfully, Colin Paul Gloster ... 15 Oct 2009 14:57
Gen3 SATA 6.0Gbps HDD simulation model
http://www.aipst.com/AIPS7100.tar.gz ... 14 Oct 2009 21:23
Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
Hi, I have a small design in VHDL with black box which i am trying to synthesize using Xilinx ISE 11.2. I get an error when running the command ngdbuild. ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, ... 13 Oct 2009 20:05
FPGA on-die LVDS termination issues
Hello, We use several source-synchronous LVDS-based interfaces in several PCB designs, such as a unidirectional interface from several multi-channel ADC devices (TI ADS725x) towards FPGA (Xilinx Virtex4 family, SX subfamily), or a full-duplex interface between high-end DSP devices (ADI ADSP-TS201S) and FPGA (Xilinx ... 16 Oct 2009 23:58
floating point operation in interrupt handler on ML403
Hi, I'm using the ML403 board for the interrupt-based system. In this system, floating point operations in interrupt handler are required and APU is employed to accelerate the single precision floating point operation. The software is running with the standalone BSP on the PPC. The snippet is shown below: // glo... 12 Oct 2009 07:21
problem while receiving negative integer in microblaze
I got the problem while receiving the value of "count" (i.e. of integer type with value positive as well as negative) in MICROBLAZE that was send from custom IP named as encoder module using "User Logic Software Register" IPIF. Encoder module counts the value of encoder pulses ranges from -5000 to +5000. I ass... 26 Oct 2009 17:48
Development boards for CPU development ?
I have a hobby project which consists of developing a complete computer system from the ground up. With complete I mean that it should have character display capabilities, keyboard input capabilities and mass storage capabilities. Graphics and networking might come in the future, but I feel that adding these is pro... 12 Oct 2009 05:11