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Trouble with Xilinx DCM - Spartan3
My apologies if this has been addressed - my web searches came up empty. I am using a DCM in a spartan3 to generate the internal clocks - a 1-X clock and a 1/2-X clock. The output of the DCM goes to a BUFG. The output of the BUFG goes to the feedback pin of the DCM, and to the rest of the logic. After init... 23 Dec 2009 15:09
GTKWave 3.3.0 for Windows is available
Hi everyone, The latest version of GTKWave (3.3.0 preliminary with TCL/TK 8.5) windows binary is available here: -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services ... 18 Dec 2009 02:54
CfP: Self-X and Autonomous Control in Mechatronics and Production
******************************************************************************** INDIN 2010 - Special Session 8th IEEE International Conference on Industrial Informatics Call for Papers Self-X and Autonomous Control in Mechatronics and Production... 16 Dec 2009 21:18
Best "bang for buck" Student Starter board for image/video processing?
Hello, all! I'm interested in exploring digital design with FPGAs for both learning purposes and to help with a senior design project I'll be working on. To start, I spent my entire 1st day of winter break (yay!) looking at different starter boards, and I'm pretty much lost. I was wondering if someone could ex... 19 Dec 2009 23:35
Best clock output pin in Spartan-3
Hello. I am using a global buffer input as clock input, the signal then goes through a DCM, and I need to output the inverted clock through a pin into another chip. Can I use any pin for this clock output or are there specific pins that better serve this purpose? Thanks. ... 15 Dec 2009 14:27
multiprocessors MB and shared BRAM
hello, I am using spartan 3 starter board (with MB7.1) to work with 2 processors cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want to add, between the two processors, a shared memory BRAM_block_v1_00_a with the controler xps_bram_if_cntlr_v1_00_a. the problem is: when I want to share the b... 16 Dec 2009 06:51
XUPV5-LX110T, DDR2, and EDK (10.1 to be precise)
Hi everyone, there has been a lot of talk about this same question I'm about to ask, but it is spread out over many different locations on the internet and I can't find a real answer... I am trying to interface the supplied 256MB DDR2 module (MT4HTF3264H-53E) with the XUPV5-LX110T board. I'm using EDK 10.1 and I can... 14 Dec 2009 04:26
Does a 1-bit mux glitch if only one input is known to change at one time?
You still will need to make sure you meet setup and hold to avoid glitches. If the system allows it would be better to put ;b; into the same clock domain. Running as fast a clock as you can can minimise this inducted jitter of an edge. With careful design and keeping it simple you could probably run a 200Mhz clo... 16 Dec 2009 04:42
Altera LP6 Logic Programming Card - Supplier
Hi Everyone, If your looking for an older Altera LP6 Logic programming card, Which is part of the PL-ASAP2 Master programming Unit, then check out this link Below. the Company is called Artisan Scientific and they have some in stock. Hope this can help some of you. 9 Dec 2009 19:58
Data2MEM - finding the blockrams after PAR?
Is there some report ISE can produce that will tell me the locations of all the blockrams it has placed? The post-PAR static timing happens to tell me that memory/r[1].ram is RAMB16_X1Y17, because that one is in a critical path, but grep through all of the generated files for memory/r[ and RAMB16_X doesn't turn up... 13 Dec 2009 23:04
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