Xilinx ISE 10.1.03
Hi all, I was just about to download the new Xilinx ISE 11.1 evaluation package. However, I was told that the new Xilinx design suite does not support Xilinx Virtex II Pro devices anymore. Does anyone have an idea where I could get hold of an old version (Xilinx ISE 10.1.03) of this package from the web sinc... 12 Jan 2010 14:02
Timing errors in Post route simulation in modelsim
Hi, when i do post route simulation i get a bunch of error similar to the following ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps, 520 ps ); # Time: 106849 ps Iteration: 0 Instance: /test_v/uut/v_ram... 12 Jan 2010 07:58
How to gracefully terminate the PCIe read request
I am using Viertex5 hardip in pcie gen1 x4 configuration. The hard IP has PCI bar register configured for 512K memory space. The Root complex is sending out the memory read request to the V5 end point with valid address (that belongs to 512K memory block). The end point sends a request to the appropriate device ... 13 Jan 2010 03:15
E1 clock problem...
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? To... 12 Jan 2010 10:38
E1 clock problem with Spartan3e...
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? T... 2 Feb 2010 14:35
I am using JTAG parallel cable to program FPGA, while programming the FPGA code into the internal flash power was disconnected and finally "PROGRAM FAILED" message was observed. I had tried to program several times but still not able to program. The observed log is below, please find it. INFO:iMPACT - Current ti... 11 Jan 2010 06:28
Solved! Why my pins were being optimized out. How do I get the firmware running now....
Secondly, if I understand correctly, the pins of my custom peripheral are being removed from the project. I've looked around the internet a bit and suspect this might be done due to auto-optimization, but considering that these pins are, indeed, being used in the user_logic It's not enough fo... 14 Jan 2010 16:54
The UK Embedded Masterclass 2010 - 6th and 11th May Cambridge & Reading
Hi, just to let you know that we are currently organising the next UK Embedded Masterclass, Visit http://www.embedded-masterclass.com Workshops include 'Migrating code to an SMP platform to get x2 performance', 'an introduction to Embedded Linux', developing 'Time Triggered code and why It Can be great cho... 9 Jan 2010 16:16
new PC specs for Xilinx tools
Hi All, I'm speccing out a new windows PC that I'll use with Xilinx tools, probably Webpack and Modelsim, and I'm looking for some advice to make sure the tools will run fast. I know memory is important, but what else? Also, what pitfalls should I watch out for? I'm not sure how relevant this info is, but I'm ... 10 Jan 2010 16:19
Difference among Virtex Families, FPGA Books
Hi Folks I have recently become very interested in FPGA and DSP. Could somebody suggest to me a newbee started book and also a related experimental board. I would also like to know the differences between the different Virtex families like Virtex 2, 4, 5 etc. Regards RK ... 8 Jan 2010 10:29