E1 clock problem...
in [FPGA]
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From: morppheu on 11 Jan 2010 11:24 Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? Today I have a process to detect if E1 F0 signals is present. If its present, I switch from internal clock to E1 clock : clk_res <= clk_int when E1_present = 0 else clk_e1; I know its a very bad design technique, but its an old code from another guy and I am looking to make the things right. What is the best way to interface with E1? Can someone help me? Thanks! --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: John_H on 12 Jan 2010 10:37 On Jan 11, 11:24 am, "morppheu" <morpp...(a)gmail.com> wrote: > What is the best way to interface with E1? The "best way" to interface to the E1 (a very low speed interface when compared to the operating speed of an FPGA) may be not to use the DCM at all but use a generic higher speed clock and transfer to/from the E1 domain across FIFOs or other asynchronous interfaces right by the I/ O, leaving the main processing to the generic, unlocked clock domain. Changing the clock source for the I/O from external to internal or vice versa can be accomplished through a BUFGMUX (since you appear to be in the Xilinx family) if you want the I/O timing to be on global clock resources.
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