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Xilinx ISE 8.2 Issue: Pin Name N1, N2...
Hello, I am seeing a problem using ISE. I have a verilog top level with pins including N0, N1, N2, N3, N4 (similar for PX, SX and MX) I add a LOC constraint in the UCF file for all pins. For some reason, the tool seems to be confused by N1, N2, N3 and N4 (but not N0, or any of PX, SX, MX) WARNING:NgdBuild:4... 4 Feb 2010 09:58
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XST is driving me mad.
I've been trying to make a _simple_ counter work, and it just doesn't. Can I get another set of eyes to look at this? It's probably something dumb/simple, but I just can't see it. The code: reg [3:0] DCM_Delay = 4'hF; reg DCM_Reset = 1'b1; always @ (posedge clk_fpga) begin if (reset) begin ... 19 Jan 2010 14:37
compiler output to fpga.
Hello, I am implementing a processor design on the virtex 2 chip. The Design was done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the design. My question is:is there a way to integrate the compiler output with the FPGA using modelsim simulator without actually programming the fpga. I am usin... 20 Jan 2010 05:05
working with ADC and DAC together
Hello I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I want to combine them together.Actually the purpose is to get an analog avlue from oscilloscope send it to FPGA(through my vhdl code for ADC ,it is converted to digital,and via the code for DAC, it will be converted to analog voltage)and che... 19 Jan 2010 11:13
Using a timer in EDK 11.
Hello, I'm trying to implement code that reads in some software registers from a peripheral after constant time intervals (ideally, a microsecond or so). I know that EDK comes with a hardware timer (xps_timer) and what I think is a software timer (fit_timer) and I know how to add them to my project as well as at... 18 Jan 2010 17:39
bit vs std_logic (was Re: Simulation of VHDL code for a vendingmachine)
Jonathan Bromley wrote: On Mon, 18 Jan 2010 17:36:07 +0100, whygee wrote: Has anyone already explored this path ? I haven't, but it has been thoroughly explored in the verification literature. Can you point me to any online paper or website about this subject ? That's one of the reasons why S... 18 Jan 2010 15:22
bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)
Hi, Gabor wrote: On Jan 17, 7:49 pm, KJ <kkjenni...(a)> wrote: In the end, it more a matter of preference than anything. If you like the format of your code using Booleans, go ahead. There are no real roadblocks to using them. In the end, the main advantage of std_logic is wit... 21 Jan 2010 12:17
Sir, I am designing DLL using DCM on VERTEX4. But I am not gwtting output for clk2x, clk2x180 I am giving my code below. I am not able to find whetre is the fault. I have written this code in architecture code, I didn't use coreIP where generates .xaw file . I tried that too but not got expected result ? ... 18 Jan 2010 09:42
HELLO .. I AM DOING A PROJECT ON IMPLEMENTING "DSSS -- BASEBAND CDMA TRANSCIEVER " ON A SINGLE FPGA ........ ANY BODY WHO HAS DONE A SIMILAR PROJECT OR IS IN THIS FIELD ..... KINDLY HELP ... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http:... 18 Jan 2010 01:00
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