FPGA
in [Hardware]
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Which WebPack for old Spartan and Spartan-2? I'm looking for a good stable version of WebPack that supports the old, Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDO ... 16 Jan 2010 18:19
Simulation of VHDL code for a vending machine On Dec 1 2009, 11:53 am, "glallenjr" <glalle...(a)gmail.com> wrote: Currently I am studying the "Circuit Design with VHDL" by Volnei A. Pedroni. On page 207 the run a simulation but do not provide the test bench. I would like to run the same simulation but I am not familiar with how to write a testbench. If p... 18 Jan 2010 10:50
CPLD programming sequence XC9500 Hello, I want to understand a few things about CPLD programming. There is a configuration sequence followed for FPGA. For e.g. XAPP188 Table 7 on page 11 shows the device configuration sequence to transfer a bit stream. Similarly, is there any sequence for CPLD XC9500? What I understood is that the .jed file ... 16 Jan 2010 09:29
Altera Quartus II on Debian GNU/Linux I want to run Quartus on my Debian computer. I see that Altera doesn't officially support Debian. Has anyone here managed to run Quartus on Debian? What was your experience? ... 18 Jan 2010 11:58
Which WebPack for old Spartan and Spartan-2? I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDO ... 15 Jan 2010 20:32
Which WebPack for old Spartan and Spartan-2? I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDO ... 14 Jan 2010 21:22
Which WebPack for old Spartan and Spartan-2? I'm looking for a good stable version of WebPack that supports the old Spartan and Spartan-2 devices for legacy product maintenance. Any recommendations? Regards; Leland C. Scott KC8LDO ... 14 Jan 2010 19:09
SystemVerilog Verification Example using Quartus and ModelSim Hello, I've been using the Quartus Simulator for many years and have recently started learning about the SystemVerilog Verification. I was hoping to find someone that has done this and is using Quartus. I am new to ModelSim and I configure Quartus to launch ModelSim to run my simulation. If anyone could provide a s... 25 Jan 2010 16:12
Virtex-5 with DDR3 running @ 50Mhz using Virtex-5 with DLL disabled and the DDR3 running at 50Mhz, do you need the terminations at the end of the fly-by routing of the address bus? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com ... 15 Jan 2010 08:13
black box module integration Dear Veterans, I have a design for FPGA whose top module includes 15 vhdl modules a flexible user/client block that interacts with these blocks . I do not have the source code for the user block. I just have the inputs and outputs of this block. I instantiated user block as a black box in my design. W... 14 Jan 2010 10:07 |