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synthesizing a completely empty design for an FPGA to measure quiescent current
Hi I want to synthesize a completely empty design, no clocks no combo and no sequential logic for a xilinx FPGA using ISE. THe problem is if I try to implement module dummy_fpga (); endmodule The tool synthesizes it but fails to translate it. I wanted to create an empty design with no inputs and no outputs and ... 4 Feb 2010 06:39
CfP: 9th International Conference on Evolvable Systems (ICES2010)
Apologies if you receive multiple postings. ======================================================== 9th International Conference on Evolvable Systems (ICES) - From Biology to Hardware St. William's College, York, UK, 5th-8th September 2010 ==============================================... 2 Feb 2010 14:35
In system memory editor of Altera for Xilinx
Hi!, I have been working with Altera FPGAs for a long time and now I have to deal with Xilinx ones. Until now, with Quartus II I have been able to manage the content of different registers and memories with 'In system memory editor' and I would like to do the same with Xilinx. I cannot find the right application to ... 2 Feb 2010 14:36
Thank you, SunMicrosystem
Hi, Sun Microsystem provides a full set of valuable resource on its webside: I printed all its documents and books about 2K pages free. I think it is the best textbooks in the world relating to building a CPU. I appreciate it very much. But there is one... 2 Feb 2010 14:35
Social Networking
------------------------------------------------------------------------------------------------------------------------------- Social Networking has been effectively used in reaching the goal of bringing down the prices of costly items through volume shopping. Go shopping with 2 Feb 2010 14:35
data transfer between PC and DE2 board
HI everyone, I'm trying to send 16 byte data block from PC to DE2 board using bulk transfer. I do modify the ReadEndpoint, WriteEndpoint and SetEndpointConfiguration to read and write 16 bytes data. But I still can't get the correct result. What had I miss? Can somebody help me? Thanks, summer ... 27 Jan 2010 20:33
VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released
The new vMAGIC release includes a number of new features, such as a new type handling system, simplified expression building, customizable VHDL output, and (finally) support for several things that have so far been missing (like VHDL package building). Also, the new version uses much less memory and performance was... 27 Jan 2010 07:00
Please help, Xilinx FIFO problem!
On Dec 23 2009, 1:28 pm, GLOW <glen.h.l...(a)> wrote: Antti, Based on all the symptoms you have described, namely the read side of the fifo going crazy and getting stale or duplicated data strongly suggests that the problem is in the recovered clock. I once worked on a chip where the duty cy... 2 Feb 2010 14:35
simulation+configuration with Ethernet Lite MAC (xilinx)
Hello all, I am trying to test configure and test one design using microbl;aze and xps_ethernetlite. I am making a testbench for the modelsim but it is doesnt work. i am trying to find a tutorial/example from xilinx but nothing how to configure the IPcore. do you have something in mind? Thank in advance all... 25 Jan 2010 15:03
Achronix FPGA
Hi all, is there anybody with experience with FPGAs from company Achronix ( I found only a few documents on their web. It looks interesting to me but I was not able to find any working contact to any sales person. I tried email to the adress on their web but nobody responded. I am hoping, tha... 28 Jan 2010 04:13
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