From: whygee on
Jonathan Bromley wrote:
> On Mon, 18 Jan 2010 17:36:07 +0100, whygee wrote:
>> Has anyone already explored this path ?
> I haven't, but it has been thoroughly explored in the
> verification literature.
Can you point me to any online paper or website about this subject ?

> That's one of the reasons why
> SystemVerilog added 2-state variables (int, bit) to the
> language; VHDL has had 2-state integer, bit and boolean
> from the outset, of course.
yes, the ADA legacy has some good advantages :-)

> There is some strong evidence to suggest that X-simulation
> is not only inconvenient because spurious Xs tend to
> chase around the design when in reality it's OK,
I've seen this too, the false positives are quite annoying :-/

> but also
> they can give rise to unjustified optimism because of
> the way certain RTL control constructs handle X inputs.
> For example, in Verilog...
> if (mode2)
> do_mode2_stuff;
> else
> do_mode1_stuff;
> If (mode2) is 1'bx in RTL simulation, the if() statement
> will take its else-branch and the simulation will act
> exactly as if (mode2) was zero.
heh, good point !

> So an alternative, which has been reported as giving
> good results, is to use 2-state simulation **but to
> randomize the values of all register variables at
> startup**. If you use different seeds for the
> randomization, you can simulate the design with a
> wide range of startup values and therefore can see
> whether it will reliably come out of reset. This
> works nicely for ASIC designs where flip-flops
> may power-up in an unknown state but the design
> is nevertheless well-behaved. Consider, for example,
> a simple clock divide-by-2 that has no reset - it
> shoudl be OK in practice, but will be stuck at X
> in a 4-state traditional simulation.
> I believe that some simulators offer this startup
> randomization as an option.
I've explored this around 2001 :-)
and I have then run into file read issues
from VHDL and compatibility issues with
different simulators. But it worked quite
well on a few platforms.

> For a nice discussion of the drawbacks of 4-state
> simulation, see Mike Turpin's survey at
> The paper discusses Verilog, but many of the same
> ideas map on to VHDL (although a lot of the details
> are different).
i'll check that, thanks !

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